Intel Corporation

Other

Sudarshan Kumar

Jiann-Cherng James Lan

Wenjie Jiang

Gaurav Mehta

Sadhana Madhyastha

Narsing Krishna Vijayrao

Vivek Joshi

Shahram Jamshidi

Jashojiban Banik

Rajesh Manglore

Sanjay Kumar

Kenneth D Shoemaker

James Steven Burns

Vivek Tiwari

Kamal J Koshy

David J Ayers

Mahadevamurty Nemani

Chi Keung Lee

James J Lan

Kai J Chin

Chung Yin Yip

Mehul Desai

Tom E Wang

Shyue L Kuo

Bharat K Bisen

Snehal Jariwala

A CAM/TCAM includes a plurality of rows of CAM/TCAM lines, a plurality of search lines, and a plurality of bit lines, wherein each row comprises an array of CAM/TCAM cells. Each TCAM cell has two storage cells, representing state for data and a mask of the cell, and match logic. The two storage cells connect to a respective bit line as input and their output drives the match logic. In response to the respective search line and storage outputs, the match logic generates cell match outputs. The match logic can be implemented using static logic comprising tristate gates and masking logic that forces the cell match output to a predetermined value in response to the stored mask value. The match outputs in the row are AND-ed by a logic tree to generate a match output, thereby reducing power consumption.

Low power content addressable memory

A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Method and apparatus to limit current-change induced voltage changes in a microcircuit

A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.

Gate-clocked domino circuits with reduced leakage current

A complementary metal oxide semiconductor (CMOS) low-power, high speed logic circuit consisting of a cascaded chain of stages. The first stage is a pulsed domino logic circuit having one or more logic signal inputs for receiving data signals, and a timing input for receiving a clocking pulse that conditions the input pulse domino stage for evaluation during a brief window of time. The output of the pulsed domino circuit is connected to a chain of series-connected skewed static logic gates, each having the channel sizes of its pull-up and pull-down transistors ratioed to a produce, from gate-to-gate in the static logic chain, alternating fast high-to-low and low-to-high transitions for the information carrying leading edge of said input data signals. The use of a pulsed domino first stage driving a chain of skewed logic static gates reduces power consumption but retains the speed of conventional domino logic circuits.

Single stage pulsed domino circuit for driving cascaded skewed static logic circuits

A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position. The apparatus comprises a multiplier with a propagate, kill, generate generator (PKG generator) coupled to it. An adder, a plus-oner, a plus-two-er and a leading zero anticipator (LZA) are each coupled to the PKG generator in parallel. A rounding control unit is coupled to the LZA and coupled to a multiplexor that outputs a result from one of the adder, the plus-oner, and the plus-two-er responsive to the rounding control unit. A normalization shifter is coupled to the multiplexor and the LZA.

Method and apparatus for improving the performance of a floating point multiplier accumulator

An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

Low power entry latch to interface static logic with dynamic logic

A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

Low power precharge scheme for memory bit lines

A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

Method and apparatus for low power memory bit line precharge

A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Multi-entry register cell

A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Method and apparatus for low power domino decoding

A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

Low power clock buffer with shared, precharge transistor

A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Method and apparatus for reducing soft errors in dynamic circuits

A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors. Each of the sustainer circuits may include a pair of back-to-back inverters.

Reducing power consumption in a data storage device

A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number of exclusive-or logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.

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Fremont, CA, United States of America

Sudarshan Kumar