Intel Corporation

Microsoft Technology Licensing, LLC

Sudarshan Bala Cadambi

Ajay V Bhatt

Jeff C Morriss

Shaun Knoll

Puthiya K Nizar

Richard M Haslam

Charles B Guy

David William Voth

Mark R Enstrom

Robert T Short

Mark A Gonzales

Philip W Martin

Narendar Bahadur Sahgal

David R Gray

Shelagh Ann Callahan

Andrew M Volk

Ralph A Lipe

Gary A Solomon

Richard Paul Mangold

Manoj Khare

Narjala Prakash Bhasker

Thomas J Hernandez

Michael J Gutmann

Jim R Trethewey

Gerald S Holzhammer

Brian J McArdle

Jeff Harness

Ralph L Lipe

Jeff Charles Morriss

Shelagh Callahan

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

M&A for exchanging date, status and commands over an hierarchical serial

A method and apparatus for automatically configuring circuit cards used in a computer system. The present invention includes a method and apparatus that enables the circuit cards to be automatically configured during system boot up without any user intervention. The present invention also includes a method for the computer system software to detect resources requested by the circuit cards in order to resolve any system resource conflicts.

Method and apparatus for automatically configuring circuit cards in a

A system for managing power consumption in a personal computer, specifically the CPU and on-board system devices. The present invention manages the power consumption of the CPU and on-board system devices (i.e., core logic) using a global event messaging scheme and an OS-Idle power event and interrupts to provide CPU power management. The CPU's low-power state is implemented such that any or a set of predetermined device interrupts will transition the CPU from low-power state to normal operation which commences at the first instruction of the interrupt handler invoked by the device interrupt. The power consumed by the platform/chipset and controller logic devices, i.e., core logic, influenced by system clocks can be managed by decreasing frequency or stopping the distributed clock(s) altogether when in low-power state. Where chipsets manage clock distribution, additional hardware mechanisms for curtailing clocks may be incorporated which can be activated by software but are de-activated automatically in hardware. A power management coordinator may be incorporated to reduce voltage spikes or sags.

Method and apparatus for managing power consumption of the CPU and

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

M&A for dynamically generating and maintaining frame based polling

Method and apparatus for exchanging data, status, and commands over an

Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

System for assigning geographical addresses in a hierarchical serial bus

A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave 'devices', employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

System having independently addressable bus interfaces coupled to

A method and apparatus for dynamically tuning a shared resource's bandwidth utilization, which enables system I/O software to control the length of burst accesses of a shared resource by peripheral components coupled to a peripheral component bus. The present mechanism enables the system I/O software to conduct empirical tests of bandwidth utilization by bus masters accessing the shared resource over the peripheral component bus. Based upon the empirical tests, the system I/O software can tune bandwidth utilization to attain a balance between peripheral component bus performance, and host bus performance.

Method and apparatus for dynamically allocating access time to a

A memory subsystem and method are disclosed in which instruction code read-prefetching is implemented in the memory subsystem itself. A single-line read-prefetch buffer is implemented in the memory subsystem. A memory controller includes an address buffer for read-prefetches, and a memory datapath includes a data buffer for read-prefetches. Smart read-prefetching is used in which only code(instruction) reads are prefetched, taking advantage of the sequentiality of code (instruction) type data as well as the page mode feature of dynamic random access memories.

Method and apparatus for efficient read prefetching of instruction code

A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to processor directed interrupt requests, processor to one processor of a group of processors interrupt requests, and processor to all processors of a group of processors interrupt requests.

Interrupt distribution scheme for a computer bus

A distributed method for arbitrating access to a common bus in a multiple processor environment is described. This method provides for fairness where multiple processors are vying for access to a global memory. An apparatus for arbitrating access to a common bus in a multiple processor environment is also described. This apparatus provides for priority determination of each processor upon system reset and provides for fairness where multiple processors are vying for access to a global memory.

Distributed arbitration method and apparatus for a computer bus using

A method of transferring data in response to a read command in a computer system having a plurality of processors coupled to an address bus, a command bus and a data bus is described. A first processor generates and sends the read command to read a first data from a second processor. The second processor then determines with which one of (1) the first data and (2) a read response command and the first data it desires to respond to the read command. If the second processor determines to respond with the first data, then it acknowledges receipt of the read command and performs an ordered response in which the command and address buses are released and only the first data is later sent to the first processor via the data bus when available. If the second processor determines to respond with the read response command and the first data, then it acknowledges receipt of the read command and performs an out-of-order response in which the access of the command and address buses is first released and gained again by arbitration when the first data is determined to be available in the second processor. The second processor then gains the access of the data bus when the data bus is free of any data transaction. The read response command and its address and the first data are then issued to the first processor.

Multiprocessor computer system with data bus and ordered and

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Portland, OR, United States of America

Sudarshan Bala Cadambi