Samsung Electronics Co., Ltd.

Sucheol Lee

Changkyu Seol

Byungsuk Woo

Youngdon Choi

Junghwan Choi

Pilsang Yoon

Myoungbo Kwak

Hyejeong So

Jiyoup Kim

Younghoon Son

Jaewoo Park

Chanik Park

Jinsoo Lim

Hyunyoon Cho

Byung-Suk Woo

Cheolmin Park

Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.

Encoding and decoding apparatuses and methods for implementing multi-mode coding

A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

Receiver receiving multi-level signal, memory device including the same and method of receiving data using the same

An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit.

Circuit configured to compensate for timing skew and operation method thereof

Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

Devices and methods for encoding and decoding to implement a maximum transition avoidance coding with minimum overhead

A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

High bandwidth memory system using multilevel signaling

A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

Receiver performing background training, memory device including the same and method of receiving data using the same

A memory device as provided may apply a pulse amplitude modulation method to data (DQ) signal transmission/reception and may scale a DQ signal according to an operating frequency condition, so as to improve data transmission performance and effectively improve power consumption. The memory device includes a memory cell array, and a data input/output circuit configured to scale a DQ signal that includes data read from the memory cell array and output the scaled DQ signal. The data input/output circuit is configured to scale the DQ signal based on an n-level pulse amplitude modulation (PAMn) (where n is 4 or a greater integer) with a DQ parameter that corresponds an operating frequency condition and output the DQ signal. Other aspects include memory controllers that communicate with the memory devices, and memory systems that include the memory devices and memory controllers.

Memory devices configured to generate pulse amplitude modulation-based DQ signals, memory controllers, and memory systems including the memory devices and the memory controllers

A receiver including: a data processing circuit, in a training mode, to compare a multi-level signal with first and second voltage signals, and to generate data density signals; a counter circuit to count the data density signals to generate counting values; a control circuit to store, in a register set, a voltage range, counting values corresponding to the voltage range and a control code associated with a first level of the first voltage signal and a second level of the second voltage signal, the voltage range being based on the first and second voltage signals; and a voltage generation circuit, in the training mode, to apply the first and second voltage signals to the data processing circuit and to increase the first level and the second level by a difference between the first and second control signals in response to the control code from the control circuit.

Receivers for performing reference voltage training and memory systems including the same

Receiver receiving multi-level signal, memory device including the same and method of receiving data using ihe same

A memory device includes: a memory cell array; a data selector configured to receive data from the memory cell array, and to output the received data as first sub-data and second sub-data; a cyclic redundancy check (CRC) generator configured to generate first CRC values corresponding to the first sub-data, and to generate second CRC values corresponding to the second sub-data; a CRC selector configured to determine an order of the first CRC values and the second CRC values, and to output one of the first CRC values and one of the second CRC values according to the determined order; and a transmitter configured to receive the first CRC values and the second CRC values according to the determined order, and to transmit CRC values of the data by a multilevel signaling method.

Memory device, data outputting method thereof, and memory system having the same

A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.

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Suwon-si, South Korea

Sucheol Lee