Motorola Corporation

Freescale Semiconductor,inc.

Sucharita Madhukar

Bich-Yen Nguyen

Ramachandran Muralidhar

Michael Alan Sadd

David L O'Meara

Sufi Zafar

Chitra K Subramanian

Bruce E White

Chun-Li Liu

Srikanth Balaji Samavedam

Frank Kelsey Baker, Jr

Clarence J Tracy

Bo Jiang

Mark Victor Raymond

Daniel T Pham

Prasad V Alluri

Roland R Stumpf

Kristen C Smith

A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

Dual metal gate transistors for CMOS process

A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.

Process of forming a semiconductor device and a semiconductor device

A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.

Device structure for storing charge and method therefore

A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements ( ) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer ( ) upon which a first gate insulator ( ) is formed. A plurality of pre-fabricated isolated storage elements ( ) is then deposited on the first gate insulator ( ). This deposition step may be accomplished by immersion in a colloidal solution ( ) that includes a solvent and pre-fabricated isolated storage elements ( ). Once deposited, the solvent of the solution ( ) can be removed, leaving the pre-fabricated isolated storage elements ( ) deposited on the first gate insulator ( ). After depositing the pre-fabricated isolated storage elements ( ), a second gate insulator ( ) is formed over the pre-fabricated isolated storage elements ( ). A gate electrode ( ) is then formed over the second gate insulator ( ), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region ( ) and a drain region ( ) are then formed in the semiconductor layer ( ) such that a channel region is formed between underlying the gate electrode ( ).

Memory device and method for using prefabricated isolated storage elements

A semiconductor memory device with a floating gate that includes a plurality of nanoclusters ( ) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate ( ) upon which a tunnel dielectric layer ( ) is formed. A plurality of nanoclusters ( ) is then grown on the tunnel dielectric layer ( ). The growth of the nanoclusters ( ) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer ( ) overlying the tunnel dielectric layer ( ). After growth of the nanoclusters ( ), a control dielectric layer ( ) is formed over the nanoclusters ( ). In order to prevent oxidation of the formed nanoclusters ( ), the nanoclusters ( ) may be encapsulated using various techniques prior to formation of the control dielectric layer ( ). A gate electrode ( ) is then formed over the control dielectric ( ), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers ( ), source and drain regions ( ) are then formed by implantation in the semiconductor layer ( ) such that a channel region is formed between the source and drain regions ( ) underlying the gate electrode ( ).

Memory device and method for manufacture

A memory cell (,), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (,) comprises a first and second current carrying electrode (,) a control electrode (,), and doped discontinuous storage elements (,). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (,), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (,).

Memory cell and method for programming thereof

A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (,) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (,) upon which a tunnel dielectric layer (,) is formed. A plurality of nanoclusters (,) is then grown on the tunnel dielectric layer (,). After growth of the nanoclusters (,), a control dielectric layer (,) is formed over the nanoclusters (,). In order to prevent oxidation of the formed nanoclusters (,), the nanoclusters (,) may be encapsulated using various techniques prior to formation of the control dielectric layer (,). A gate electrode (,) is then formed over the control dielectric (,), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (,), source and drain regions (,) are then formed by implantation in the semiconductor layer (,) such that a channel region is formed between the source and drain regions (,) underlying the gate electrode (,).

Growing community of inventors

Austin, TX, United States of America

Sucharita Madhukar