Sony Corporation

Sony Electronics Inc

C-cube Microsystems, Inc.

Other

Sony Electronics Inc., Jointy

Subroto Bose

Shirish C Gadre

Taner E Ozcelik

Moshe Bublil

Stephen C Purcell

Syed Reza

John Hong

Edward J Paluch

Didier J Le Gall

Sabyasachi Dutta

A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.

Variable length decoder for decoding digitally encoded video signals

A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8&times;8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16&times;16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.

Motion compensated digital video decoding and buffer memory addressing therefor

A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8.times.8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16.times.16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.

Motion compensated digital video decoding with buffered picture storage

A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives. To further reduce instruction latency, if an instruction makes use of the contents of a register that is in the process of being written by an immediately preceding instruction, the RISC CPU 'bypasses' the register file, using previous results directly in a subsequent instruction. For the purposes of control and debugging, the PC can be read or written by an external host, and instructions can be loaded directly from the host. Also, pages of instructions can be loaded to or from the instruction memory to allow for an unlimited virtual instruction memory space.

Special purpose processor for digital audio/video decoding

A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.

Run level pair buffering for fast variable length decoder circuit

A structure and a format for providing a video signal encoder under the MPEG standard are provided. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements DCT and IDCT and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a 'patch' of eight motion vectors at a time.

2-dimensional memory allowing access both as rows of data words and

Motion vector encoding circuit and method thereof

A structure and a format provide a video signal encoder under the MPEG (Motion Picture Experts Group) standard. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embodiment, the central processing unit (CPU) and multiple coprocessors implements discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) and other signal processing functions, generating variable length codes, and provides motion estimation and memory management. The instruction set of the central processing unit provides numerous features in support for such features as alpha filtering, eliminating redundancies in video signals derived from motion pictures and scene analysis. In one embodiment, a matcher evaluates 16 absolute differences to evaluate a 'patch' of eight motion vectors at a time.

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Santa Clara, CA, United States of America

Subroto Bose