Texas Instruments Corporation

Subrato Roy

Ankur Chauhan

Md Abidur Rahman

Sanjeev Praphulla Chandra Nyshadham

Sudheer Prasad

Dattatreya Baragur Suryanarayana

Aalok Dyuti Saha

Vishal I Gupta

Sumantra Seth

Abhishek Kumar

Eung Jung Kim

Kushal D Murthy

Vijay Krishnamurthy

Min Chu

Vinayak Hegde

Abhrarup Barman Roy

Tikno Harjono

Gary Eugene Daum

Abhijeet Gopal Godbole

Kuntal Joardar

Abhinay Patil

Sathish Vallamkonda

Deepak Verma

Harsh Patel

Gaurav Kumar Mittal

Vasishta Kidambi

Dilip Kumar Jain

One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.

Turn on delay measurements for capacitive load

In described examples, a circuit includes a first current mirror circuit. The first current mirror circuit is coupled to a power input terminal. A first stage is coupled to the first current mirror circuit, and a second stage is coupled to the first stage and to the first current mirror circuit. An amplifier is coupled to the first and second stages. The amplifier has first and second input terminals. The first input terminal is coupled to the first stage, and the second input terminal is coupled to the second stage. A second current mirror circuit is coupled to the first stage, the second stage and the amplifier.

Low noise bandgap reference architecture

One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.

Power switch reverse current protection systems

One example includes a method for measuring a quiescent current in a switching voltage regulator. The method includes generating a mathematical model of a circuit design associated with the switching voltage regulator. The mathematical model includes measurable parameters to describe a switching current of a power switch of the switching voltage regulator. The method also includes fabricating a circuit comprising the switching voltage regulator based on the circuit design. The fabricated circuit includes the power switch and conductive I/O. The method also includes coupling the conductive I/O of the fabricated circuit to a circuit test fixture and providing electrical signals to the conductive I/O via the circuit test fixture. The method also includes measuring the measurable parameters in response to the electrical signals and applying the measurable parameters to the mathematical model to calculate the switching current. The method further includes calculating the quiescent current based on the switching current.

Method for measuring quiescent current in a switching voltage regulator

Methods, apparatus, systems and articles of manufacture are disclosed for preventing undesired triggering of short circuit or over current protection. An example apparatus includes an output terminal; a voltage detection device coupled to a voltage detection input terminal and the output terminal and including a voltage detection output coupled to a logic gate first input terminal; a pulse extender coupled between a logic gate output and a selecting node; a multiplexer coupled to the selecting node and configured to be coupled to a first protection circuit, a second protection circuit, and a driver; and a switch coupled between an input terminal and the output terminal and including a switch gate terminal coupled to the driver.

Methods and apparatus to prevent undesired triggering of short circuit or over current protection

An apparatus includes an output transistor device configured to control an output voltage of an output node in response to a control signal and an input voltage. A current sensor is configured to sense an output current supplied from the output node. A feedback converter is configured to convert the sensed output current to a feedback signal that tracks the output voltage of the output node. The feedback converter is further configured to set a clamping threshold. A gate control circuit is configured to generate the control signal in response to the feedback signal. The gate control circuit is configured to clamp the output voltage of the output node via the control signal based on the clamping threshold.

Over-voltage clamp circuit

The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.

Configurable retry for system operations

An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

Power transistors with a resistor coupled to a sense transistor

An apparatus includes: a first power transistor having a first current conduction path coupled between an input for receiving a supply voltage and a node and a first gate terminal coupled to a first gate control signal; a second power transistor having a second current conduction path coupled between the node and an output terminal for supplying a load current to a load; and a second gate terminal coupled to a second gate control signal; and a current sense transistor having a third gate terminal coupled to the first gate control signal, and outputting a sense current. The apparatus further includes: a differential amplifier having an output signal, and a feedback transistor having a gate terminal coupled to the output signal of the differential amplifier; and a resistor coupled between a monitor node and ground.

Current sensing and control for a transistor power switch

An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

Controlling current limits in current limiting circuits

A bandgap reference voltage generator includes a first and a second bipolar junction transistor, which is biased at a lower current per unit emitter area than that of the first transistor. Accordingly, the base to emitter voltage of first transistor is higher than that of the second transistor and a delta VBE is generated at the base of the first transistor with respect to the base of the second transistor. A first voltage divider generates a divided voltage of a VBE (fractional VBE) at a first center node. The fractional VBE is added to the VBE of the first transistor and subtracted from the VBE of the second transistor by closed loop feedback action to generate a temperature compensated reference voltage at the base of second transistor. The reference voltage can be amplified to higher voltage levels by using a resistor divider at the base of second transistor.

Bandgap voltage generation

The disclosure provides a voltage regulator for generating piece-wise linear regulated supply voltage. The voltage regulator includes a first clamp circuit that receives a reference voltage and an analog supply voltage. A second clamp circuit receives the reference voltage. A voltage divider circuit is coupled to the first clamp circuit and the second clamp circuit. The voltage divider circuit receives a peripheral supply voltage and generates a regulated supply voltage.

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Bengaluru, India

Subrato Roy