Intel Corporation

Subratakumar Mandal

Fangxing Wei

Mirza Jahan

Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator

A novel digital eye width monitor (DEWM) system and method are disclosed. The DEWM system provides on-die capability to directly measure the left and right eye-width in picoseconds. The DEWM system measures the time from the phase interpolator (PI) clock position (data eye center, left edge, right edge) to a reference clock, and calculates the left and right eye width within a single-digit pico-second level of accuracy.

Gated ring oscillator-based digital eye width monitor for high-speed I/O eye width measurement

An embodiment of the invention includes dynamically adjusting gain peaking of circuit logic such that error rates are acceptable across various process/voltage/temperature (PVT) ranges. An embodiment uses PVT dependant programming, such as but not limited to resistance compensation (RCOMP) codes, to control impedance compensation logic, such as but not limited to a Continuous Time Linear Equalization (CTLE) circuit. The PVT programming may be used to control gain peaking amplitude and gain peaking frequency across ranges of different PVTs. As a result, error performance is not impaired across different PVT corners and gain peaking is more consistent across different PVT corners. Other embodiments are included herein.

Dynamic adaptation of continuous time linear equalization circuits

According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer. The input signal is strengthened by a factor that corresponds to a control signal. The control signal is derived from an output signal of an impedance control unit that is used to compensate for variations in the buffer's performance conditions. The output signal of the impedance control unit has a range of values corresponding to variations in the buffer's performance conditions. The control signal has a range of values that is larger than the range of values associated with the output signal of the impedance control unit.

Growing community of inventors

Portland, OR, United States of America

Subratakumar Mandal