Motorola Corporation

Subramoney V Iyer

Rajeev Bajaj

Rajan Nagabushnam

Chitra K Subramanian

Olubunmi O Adetutu

James D Hayden

Bradley Paul Smith

David K Watts

Kevin G Kemp

Percy V Gilbert

Matthew A Thompson

Sanjit K Das

Asanga H Perera

Mark G Fernandes

Jaime A Saravia

Shyam Mattay

Rajive Dhar

Thom Kobayashi

Ram Venkataraman

Vibrating and oscillating rates can be dynamically changed during polishing to achieve an optimal polishing process. A semiconductor device substrate (34) has a first layer with a first film (12) and a second film (10) that overlies the first film (12), where the first film (12) is harder and underlies the second film (10). In one embodiment, the substrate (34) is placed over a first region (66) of a polishing pad (60). The second film (10) is polished at a first vibrating and oscillating rates over the first region (66). An endpoint signal is received when the first film (12) is reached. The substrate (34) is moved to a second region (62) of the polishing pad (60) that is closer to the edge of the pad and has a higher feature density compared to the first region (66). Polishing is performed at a second vibrating and oscillating rates that are different from the first vibrating and oscillating rates to remove the first film (10).

Process for forming a semiconductor device

A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along with slurry (22) containing silica and an acidic based oxidizer such as oxadic acid in a chemical mechanical polishing (CMP) process. The result is less than 5:1 and preferably 1:1. This low selectivity results in the metal layer (20) being polished to a level below the surface of the surrounding oxide in a timed-controlled polish.

Low selectivity chemical mechanical polishing (CMP) process for use on

A method for forming a contact structure (10) which enables the use of ultra-shallow source/drain junctions begins by forming source and drain regions (14) and gate electrode (16). The source and drain regions (14) and the gate electrode (16) are silicided to form silicide regions (20). A conductive tungsten nitride etch stop layer (22) is formed overlying the silicide regions (20). Contact plug regions (28) are then formed to contact to the etch stop layer (22) and silicided regions (20). At this point, all of the silicide regions (20) are electrically short circuited. To remove this electric short circuit, an isotropic etch process comprising hydrogen peroxide, ammonium hydroxide, and water is used to remove portions of the tungsten nitride regions which are between the individual contact portions (28) in a self-aligned manner.

Method for using a conductive tungsten nitride etch stop layer to form

A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).

Integrated circuit having a dummy structure and method of making

A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.

Method for polishing a semiconductor wafer using dynamic control

A process for polish planarizing a fill material (40) overlying a semiconductor substrate (30) includes a multi-step polishing process. In one embodiment, a second planarization layer (42) is deposited over a fill material (40) and a portion of the fill material (40) is removed leaving a remaining portion (44). The pad pressure of a CMP apparatus (20) is adjusted such that a first pressure is generated during the polishing process. Then, the remaining portion (44) is removed, while operating the CMP apparatus (20) at a second pad pressure. The selectivity of the polishing process is maintained by reducing the pad pressure during the second polishing step. In a second embodiment, after the first polishing step is performed, the remaining portion (44) is removed by an etching process using a portion (46) of second planarization layer (42).

Multi-step planarization process using polishing at two different pad

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Austin, TX, United States of America

Subramoney V Iyer