Oracle International Corporation

Subramanian Venkateswaran

Alexander Korobkov

Rupesh Verma

Jay J Zhu

Wai Chung William Au

Anuj Trivedi

Yao-Cheng Tien

Wai Chung W Au

Techniques are provided for improving performance of spatial queries by defining a grid that divides the domain space into cells, and then using a cell-to-item mapping to determine which items do not have to be individually evaluated against the location criteria of the spatial queries. Based on the cell to which an item belongs, the item may automatically qualify as a match, be automatically disqualified, or require item-specific evaluation. To account for items with size, the query window of a spatial query may be expanded. To limit the degree to which the query window is expanded, a plurality of grids may be established for the domain space, where each grid has differently sized cells, and items are assigned to grids based on the size of the items.

Hierarchical grid for spatial querying

Techniques herein are for generating geometric models. A method involves receiving a raw data set. Generation parameters include an abstraction function, a raw data set, a plurality of size pairs, and a quality interval. Each size pair comprises a view size and a portion size. The view size comprises an amount of display area. The portion size comprises an amount of raw data. For each size pair, associate a set of grid square sizes with the size pair. Each grid square size comprises a multiple of natural units. The quality interval contains a multiplicative product of the grid square size times a ratio of the view size to the portion size. Generate a set of geometric models based on the raw data set, the plurality of size pairs, the abstraction function, and the set of grid square sizes associated with the plurality of size pairs.

Geometric model for visually debugging massive spatial datasets

A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation run. The fundamental time steps are generated when changes that indicate state time derivatives during two or more successive integration steps are within a predetermined range. The system stores the one or more fundamental time steps as fundamental circuit events in an events queue, and updates the parameters for the plurality of devices based on the fundamental circuit events to generate one or more derivative circuits. The system then performs one or more derivative circuit simulation runs using the derivative circuits.

Integrated circuit simulation using fundamental and derivative circuit runs

Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

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Santa Clara, CA, United States of America

Subramanian Venkateswaran