Advanced Micro Devices Corporation

Subramanian Narasimhan

Ronald C Laugesen

Nallepilli S Ramesh

For each channel, a pair of buffers permits 'non-slip' transfer of data signals on and off a bus synchronized with signals on a time-division multiplexed pulse-code modulation (PCM) highway. A source buffer consisting of a serial-in, parallel-out register and two parallel-in, parallel-out registers receives signals from one of the PCM channels and transmits these signals onto a bus synchronized with a data-routing multiplexer employed within a digital exchange controller employing the device. A destination buffer consisting of two parallel-in, parallel-out registers and a parallel-in, serial-out register receives signal from the bus and, in conjunction with a transmit multiplexer, generates the signals on the PCM highway.

Time-slot assigner multiplexer

Method and apparatus for rapid, low-jitter acquisition of a clock signal at a serial communication port. In the absence of communication over the port, and during clock acquisition, a free-running clock is generated for local communication. Following clock acquisition by a circuit which performs coarse phase adjustments, a simple logic network generates refined phase adjustment signals which drive a variable, nominal divide-by-32, counter so that the clock generated thereby is smoothly brought into synchronization with the acquired clock in one bit increments. In a typical application, at most 48 bit periods at the port are required to synchronize the clock, with a clock phase jitter of less than 1.1%.

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Santa Clara, CA, United States of America

Subramanian Narasimhan