Advanced Micro Devices Corporation

Subramanian N Venkatkrishnan

Tho Le La

Mark T Ramsbey

Kathleen R Early

Jack F Thomas

Dawn M Lee

Minh Van Ngo

Steven C Avanzino

Darin A Chan

Diana M Schonauer

Pei-Yuan Gao

Richard E Lamm

Christy Mei-Chu Woo De La Girond'arc

A method of decorating a semiconductor substrate with an etchant solution is provided for revealing defects, such as microscratches, resulting from an oxide chemical-mechanical planarization (CMP) polishing. An oxide layer is provided over the substrate made from, for example, tetraethylorthosilicate (TEOS). The oxide layer is polished by a CMP process which tends to leave behind microscratches and other defects that can cause conductivity problems on the wafer. To reveal the microscratches, the wafer is decorated or submerged in an etchant, such as an HF etchant, for a period of time. Following the decorating, the wafer is rinsed, dried and inspected. The method improves the ability to identify and optimize steps in a semiconductor fabrication process that cause semiconductor defects.

Method of inspecting a semiconductor wafer for defects

A multiple-layer interconnect structure in an integrated circuit, is formed using damascene techniques. A first layer interconnect has a first dielectric layer through which at least one first layer conductor extends. A second layer interconnect is then formed on the first layer interconnect. The second layer interconnect also includes a second layer dielectric through which at least one second layer conductor extends. However, the second layer interconnect is created by first forming a thick second later dielectric layer and then reducing the thickness of the second layer dielectric prior to a patterning step. As a result topographical irregularities that may have carried over to the second layer interconnect from the first layer interconnect are removed by providing a substantially planar surface on the second layer dielectric.

Elimination of residual materials in a multiple-layer interconnect

The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.

Doubled-sided wafer scrubbing for improved photolithography

The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by polishing the wafer backside prior to photolithography. It was found that particles adhering to and/or scratches on the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Backside polishing, as by chemical-/mechanical polishing, removes such adhering particles and/or scratches, thereby improving photolithographic accuracy.

Backside wafer polishing for improved photolithography

Planarization of a patterned semiconductor wafer is effected by chemical-mechanical polishing using a carrier assembly comprising a carrier film adhesively bonded to a base plate, preferably by a pressure sensitive adhesive. Chemical-mechanical polishing is preferably conducted employing three phases of different pressures to prevent wafer slippage.

Chemical-mechanical polishing of thin materials using non-baked carrier

Uniform planarization of a patterned semiconductor wafer is effected with a chemical-mechanical polishing apparatus containing a base plate comprising a convex surface portion.

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Sunnyvale, CA, United States of America

Subramanian N Venkatkrishnan