Agere Systems Inc.

Subramanian Karthikeyan

Sailesh Mansinh Merchant

Seung Hyuk Kang

Kurt George Steiner

Scott Jessen

Robert Y S Huang

Joseph Ashley Taylor

Isaiah O Oladeji

Lisa E Mullin

Joshua Jia Li

A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.

Semiconductor test device with heating circuit

Method and test structures for determining heating effects in a test semiconductor device () are provided. The test device may include a first conductive metal structure (-) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (-) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

Test semiconductor device and method for determining Joule heating effects in such a device

An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.

Semiconductor device having reduced intra-level and inter-level capacitance

A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Mask layer and dual damascene interconnect structure in a semiconductor device

Method and test structures for determining heating effects in a test semiconductor device () are provided. The test device may include a first conductive metal structure () for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate () the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.

A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

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Schnecksville, PA, United States of America

Subramanian Karthikeyan