Texas Instruments Corporation

Subramanian Jagdish Narayan

Swaminathan Sankaran

Keith Edmund Kunz

Russell Carlton McMullan

Anand Subramanian

Binu Kamblath Pushkarakshan

Vadim Valerievich Ivanov

Anand Kannan

Krishnamurthy Ganapathi Shankar

Dipankar Mandal

Janakiraman Seetharaman

Kiran Godbole

Chandana Krishna

Mahadevan Venkiteswaran S

Sachin S

Madhuresh Sinha

In examples, an input/output (I/O) circuit comprises an input, an output, and a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal coupled to the input. The circuit also includes a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to ground and the fourth current terminal coupled to the second current terminal. The circuit further includes a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the third transistor coupled between the input and the output and the third control terminal coupled to the second current terminal.

Reducing back powering in I/O circuits

A gate driver includes a gate current circuit and a driver logic circuit. The gate current circuit has a gate current circuit output and includes first and second current sources coupled to the gate current circuit output. The driver logic circuit has a capacitor and is configured to: charge and discharge the capacitor to generate a detect voltage across the capacitor; cause the first current from the first current source to flow to the gate current circuit output in response to a voltage on the gate current circuit output being below the detect voltage; and cause the second current from the second current source to flow to the gate current circuit output in response to the voltage on the gate current circuit output being above the detect voltage.

Gate driver with feed forward control of gate current

A multi-stage analog-to-digital converter includes a signal input terminal, a first stage analog-to-digital converter, a digital-to-analog converter; a second stage analog-to-digital converter, and dither circuitry. The first stage analog-to-digital converter includes an input coupled to the signal input terminal. The digital-to-analog converter includes an input coupled to an output of the first stage analog-to-digital converter, and an input coupled to the signal input terminal. The second stage analog-to-digital converter includes a first input coupled to an output of the digital-to-analog converter. The dither circuitry is coupled to a second input of the second stage analog-to-digital converter, and is configured to provide a dither signal to the second stage analog-to-digital converter during selection of fewer than all bits of a digital value of a residue signal received from the digital-to-analog converter.

Dithering and calibration technique in multi-stage ADC

A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

Embedded tungsten resistor

The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage.

Method and apparatus for a brown out detector

Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

Frequency detector and oscillator circuit

A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.

Adding predefined offset to coarse ADC residue output to SAR

Offset calibration technique to improve performance of band gap voltage reference. An example of a bandgap reference source includes an output resistor, a first and second transistors and a differential amplifier. A positive-input calibration phase switch is in communication with a positive amplifier input, a emitter of the first and second transistor and a negative-input calibration phase switch in communication with the negative amplifier input, the emitter of the first and second transistor. A positive-output calibration phase switch is in communication with the positive amplifier output, the first and second terminal of the output resistor and a negative-output calibration phase switch is in communication with the negative amplifier output, the first and second terminal of the output resistor. An adjustable resistance is in communication with the emitter of the first transistor, the emitter of the second transistor, and the second terminal of the output resistor.

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Bengaluru, India

Subramanian Jagdish Narayan