Synopsys, Inc.

Subramanian Chebiyam

Rohit Kapur

Anshuman Chandra

Santosh Shripad Kulkarni

Jyotirmoy Saikia

Neeraj Surana

Parthajit Bhattacharya

Chandramouli Gopalakrishnan

An automated visualization tool in a command line environment allows complex log data to be represented by symbols and associated information for clarity of communication and better understanding of the associated design.

Automatically generated schematics and visualization

A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided.

Command coverage analyzer

A method for masking scan chains in a test circuit of an integrated circuit is disclosed. The test circuit includes multiple mask banks. Different mask patterns are stored in each of the mask banks. A first mask bank of the multiple mask banks is selected and the mask pattern stored in the selected first mask bank is used for masking the output of the scan chains of the test circuit during a first portion of a test cycle. A second mask bank of the multiple mask banks is selected and the ask pattern stored in the selected second mask bank is used for masking the output of the scan chains of the test circuit during a second portion of the test cycle.

Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

Operating a scan chain of a test circuit of an integrated circuit to have either a single fanout or multiple fanout to a compressor. The test circuit receives a fanout control signal for configuring the fanout of the scan chain. If the fanout control signal indicates configuring of the scan chain with a single fanout, the output of the scan chain is sent to one input of a compressor. If the fanout control signal indicates configuring of the scan chain with multiple fanout, the output of the scan chain is sent to multiple inputs of the compressor.

Scheme for masking output of scan chains in test circuit

A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit.

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Sunnyvale, CA, United States of America

Subramanian Chebiyam