Synopsys, Inc.

Subrahmanya Narasimha Murthy Palla

Subramanyam Sripada

Ajit Sequeira

A mode of a circuit design is simplified by eliminating clocks and corresponding timing exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding timing exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on a comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding timing exceptions. The modified mode is used for performing timing analysis.

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Hyderabad Telangana, India

Subrahmanya Narasimha Murthy Palla