Qualcomm Incorporated

Subodh Singh

Avinash Philip

Sankaran Nampoothiri

Thomas Andrew Sartorius

Girish Bhat

Victor Wong

Abhishek Ranka

Kapil Bansal

Pradeep Atur

ShankarGanesh Kandasamy

Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

Power reduction via memory efficiency compensation

Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.

Increasing caching efficiency using cache data patterns

One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

System and method for preserving critical debug data in a portable computing device

A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.

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Bengaluru, India

Subodh Singh