Fujitsu Corporation

Subodh M Reddy

Rajeev Murgai

William Warren Walker

Kanji Uchino

Takeshi Horie

Takashi Miyoshi

Toshiyuki Shibuya

Gustavo R Wilke

Ranjeez Murgai

Mehdi B Tahoori

According to an aspect of an embodiment, a method of providing a virtual class includes providing access to temporally-dimensioned educational material to participants of the virtual class in a social network. The method may also include capturing supplemental material generated by the participants interacting with each other in real-time in the social network. The method may also include associating the supplemental material with a range of relative time within the temporally-dimensioned educational material. The method may also include providing the temporally-dimensioned educational material to a client device associated with a participant of the virtual class. The method may also include providing the supplemental material to the client device for presentation at the client device during the range of relative time within the temporally-dimensioned educational material.

Dynamic evolving virtual classroom

A graph database is described. The graph database includes one or more symbolic data stores and one or more key-value data stores. Each symbolic data store is configured to symbolically store sets of multiple hyper-graph nodes. Each key-value data store is configured to store attribute information for hyper-graph nodes and hyper-graph edges.

Symbolic hyper-graph database

In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

System and method for clock network meta-synthesis

A method includes storing content graph information regarding individual items of content accessed by one or more users of a system, storing path graph information comprising the order in which each of the one or more users accessed individual items of content, and selecting individual items of content to be presented to a subsequent user of the system and an order in which such individual items of content are presented to the subsequent user based on the stored content graph information and the stored path graph information.

System and method for content storage and retrieval

According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components.

Designing analog circuits

A method may include generating logical transition data for the logic cell based on an analysis of a digital model for the logic cell, the logical transition data including at least one entry indicative of an output transition of the logic cell occurring in response to an input transition of the logic cell. The method may also include generating a parameterized transition based analog model for the logic cell, the parameterized transition based analog model including transition timing parameters associated with each entry of the logical transition data. The method may further include generating an analog model for the logic cell based on the parameterized transition based analog model and one or more analog netlists characterizing the logic cell.

Transition-based macro-models for analog simulation

A system and method for constructing a clock tree based on replica stages is described. The system and method may comprise determining a size of an input buffer for driving a load capacitance of the output buffer based on a fanout, determining a wire width and a wire length based on the size of the output buffer, the fanout and a replica stage mathematical model, and connecting the output buffer and the corresponding input buffer to a conductor routed on one or more predetermined metal layers and having the wire length and the wire width. The conductor is placed within ground shields having a fixed width.

Constructing a replica-based clock tree

A method of analyzing timing uncertainty involves creating an accurate model of one or more circuit elements of a mesh circuit residing within a window that covers a subset of the mesh circuit. An approximate model of one or more circuit elements of the mesh circuit residing outside of the window is also created. Monte Carlo simulations are performed on the combination of the accurate model and the approximate model to determine a plurality of timing values, wherein each run of the Monte Carlo simulation varies one or more parameters potentially affecting the operation of the mesh circuit. An uncertainty associated with the circuit elements is determined, based at least in part on the plurality of timing values. One embodiment considers clock as the signal whose timing uncertainty can be determined. Other embodiments model and simulate the global drive circuit that drives the mesh circuit separately from the mesh circuit to take into account common path correlations in the drive circuit.

Analyzing timing uncertainty in mesh-based architectures

A method is provided and includes accessing a description of a chip, which includes sequential elements and a clock mesh. Items used include: the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh. Additionally, the method includes determining a plurality of original window locations covering the clock mesh. Further, for each original window location, the method includes expanding the original window location in one or more directions to generate a larger window location; generating a mesh simulation model inside the larger window location; simulating the mesh simulation model; measuring clock timing for the sequential elements in the original window location based on the simulation of the mesh simulation model; and collecting timing information on all the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.

System and method for providing an improved sliding window scheme for clock mesh analysis

In one embodiment, a method includes accessing a description of a chip including multiple sequential elements and a clock mesh, information for modeling the sequential elements and interconnections, and a set of parameters of the clock mesh. The method also includes, using the description of the chip, the information for modeling the sequential elements and interconnections, and the set of parameters of the clock mesh, determining multiple original window locations covering the clock mesh. Each window location includes one or more of the sequential elements on the chip. The method also includes, for each original window location, expanding the original window location in one or more directions to generate a larger window location and generating a mesh simulation model including a detailed model inside the larger window location and an approximate model outside the larger window location, simulating the mesh simulation model, and measuring clock timing for the sequential elements in the window location based on the mesh simulation model. The method also includes collecting timing information on the sequential elements on the chip based on the measured clock timing for the sequential elements in the original window locations.

Border-enhanced sliding window scheme (SWS) for determining clock timing in a mesh-based clock architecture

In one embodiment, a method for computing current in a digital circuit based on an accurate current model for library cells includes accessing a cell library, for each cell in the cell library corresponding to a cell in a digital circuit, generating multiple waveforms of current drawn by the cell from a power supply according to one or more predetermined values of one or more input parameters of the cell, analyzing the digital circuit to determine one or more actual values of the input parameters of each cell in the digital circuit, for each of the cells in the digital circuit, generating a current waveform according to the determined actual values of the input parameters and a waveform of current drawn by the cell from the power supply generated by the characterization module corresponding to the determined actual values of the input parameters, and summing the current waveforms of the cells in the digital circuit to generate a waveform of current drawn by the digital circuit from the power supply for use in a pattern-dependent methodology (PDM) or a patten-independent methodology (PIM).

Computing current in a digital circuit based on an accurate current model for library cells

In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.

Growing community of inventors

San Jose, CA, United States of America

Subodh M Reddy