Nvidia Corporation

Samsung Electronics Co., Ltd.

Indian Institute of Technology

All India Institute of Medical Sciences

Subodh Kumar

Prem K Kalra

Mayank Jain

Justin S Legakis

Jonathan J Dunaisky

Nishant Bugalia

Ramandeep Singh

Sneh Anand

Sanjiva Prasad

Vinkle Kumar Srivastav

Kolin Paul

Ashish Suri

Aman Taneja

Subhashis Banerjee

Britty Baby

John Malcolm Neil

An electro-mechanical box trainer for neurosurgery comprise: (i) a base part which comprises a rubberized working port () for insertion of endoscope () and tool () for manipulation, a microcontroller programmed motorized peg plate () placed at 45&#xb0; degrees of inclination for defining a practice volume according to the neuroendoscopy, a membrane keypad to change the angle of rotation of said peg plate () along vertical axis, liquid crystal display (LED) array to illuminate the interior of the box and a removable base plate () to house the circuitry; and (ii) a removable part enclosed of five walls such as a front wall (), two lateral walls (and), a back wall () and a top wall (), comprises a housing to mount an auxiliary camera () to record all the task for evaluation and a slider at the back to adjust the camera focus.

Neuro-endoscope box trainer

A method for generating an environmental profile is provided. The method for generating environmental profile includes generating an image of an environment by capturing the environment with at least one recording device, detecting a change of an object in the environment based on the image, and generating an environmental profile based on the change of the object.

Method and apparatus for environmental profile generation

A system and method for dividing three-dimensional patches into tasks for processing receives control points defining a three dimensional patch and determines if a number of vertices of the three dimensional patch is greater than a maximum value. When the number of vertices is not greater than the maximum value, the three dimensional patch is output as a single task. When the number of vertices is greater than the maximum value, the three dimensional patch is divided into multiple tasks that each include a number of vertices that is not greater than the maximum value and the multiple tasks are output.

Distributed tessellation topology generator

A system, method, and computer program product are provided for validating a graphics processor design. In operation, a test image is identified. Additionally, a reference image is automatically selected from a set of reference images. Furthermore, a graphics processor design is validated using the test image and the selected reference image.

System, method, and computer program product for validating a graphics processor design

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New Delhi, India

Subodh Kumar