International Business Machines Corporation

Universiti Brunei Darussalam

Subhrajit Bhattacharya

Daniel Lawrence Ostapko

John A Darringer

Stephen Victor Kosonocky

Anthony Correale, Jr

Ruchir Puri

William Robert Lee

Daniel Ray Knebel

Yogish Sabharwal

Umamaheswari C Devi

Raghavendra Singh

Nathaniel Douglas Hieter

Nilanjan Banerjee

Veena S Pureswaran

Stephen J Barnfield

Reinaldo A Bergamaschi

Jean-Marc Daveau

Sambuddha Roy

Vanessa Teo

Reinaldo A Bergamashi/Rab

Jayasuriya M R Sarath Bandara

Methods, systems, and computer program products for scheduling crop transplantations are provided herein. A method includes determining one or more lifecycle constraints associated with a given crop via analysis of crop data; determining one or more cultivation conditions constraints associated with cultivating the given crop via analysis of cultivation conditions data; determining one or more weather forecast constraints associated with a given geographic area via analysis of weather forecast data; and generating a transplantation schedule for the given crop in the given geographic area based on determining a fit across (i) the one or more lifecycle constraints, (ii) the one or more cultivation conditions constraints, and (iii) the one or more weather forecast constraints.

Scheduling crop transplantations

One embodiment provides a method of identifying a location of a target object within a plurality of images, the method including: utilizing at least one processor to execute computer code that performs the steps of: receiving a plurality of images; receiving position information indicating a central location, wherein the central location comprises a location that the plurality of images were taken; receiving direction information indicating a position of a target object with respect to the central location, wherein one of the plurality of images contains the target object; and determining, using the position information and the direction information, a target location, wherein the target location comprises a location of the target object. Other aspects are described and claimed.

Verification of business processes using spatio-temporal data

A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.

System for using partitioned masks to build a chip

A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.

Modeling and simulating a powergated hierarchical element

An improved solution for designing a circuit is provided. A set of target paths, each of which has a performance attribute that is targeted for improvement, is obtained from a design for the circuit. An influence for one or more of the nodes in the set of target paths is obtained. One or more of the nodes are selected for improvement using the influence. Subsequently, the performance attribute for each selected node is improved. For example, an implementation of the node can be replaced with an implementation having an improved performance attribute. The relative improvement provided by an alternative implementation versus a relative detriment to another performance attribute can be obtained and used in selecting the node(s) for improvement. In one embodiment, the relative improvement and influence are used to obtain a sensitivity metric for each alternative implementation, which is used in selecting the node(s) for improvement. In this manner, the circuit can be improved in a more effective manner.

Influence-based circuit design

A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of NNFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of NNFETs are scanned and perform the function of voltage clamps and the remaining (N&#x2212;N) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nbased upon testing of the manufactured integrated circuit.

Power gating techniques able to have data retention and variability immunity properties

A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A method is provided comprising printing a set of component cores onto a die at predetermined locations with a reusable mask set; providing a custom blocking mask that includes opaque regions that positionally correspond with the component cores on the die; superimposing the custom blocking mask with a generic array type cell mask to form superimposed masks; and using the superimposed masks to print generic array type cells onto the die with the exception of the predetermined locations where the set of component cores reside.

Method for using partitioned masks to build a chip

A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail, the virtual rail voltage clamp comprising at least one NFET. A total of NNFETs are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices. A quantity of NNFETs are scanned and perform the function of voltage clamps and the remaining (N-N) NFETs perform power gating. Manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity Nbased upon testing of the manufactured integrated circuit.

A method and algorithms for creating correct-by-construction interconnections among complex intellectual property (IP) cores with hundreds of pins. The methods contemplated herein significantly reduce the time, complexity and potential for errors associated with systems-on-chip (SoC) integration.

Methods and arrangements for automatically interconnecting cores in systems-on-chip

Processes and arrangements for describing a system-on-chip at an abstract level. Contemplated is the creation of a &ldquo;virtual design&rdquo; and its automatic synthesis into a &ldquo;real design that includes IP blocks from a library as well as all required interconnections and interface logic between them. Significant reductions in the complexity, time and cost associated with system-on-chip designs can be enjoyed as a result.

Growing community of inventors

White Plains, NY, United States of America

Subhrajit Bhattacharya