Leland Stanford Junior University

Commissariat a L'energie Atomique Et Aux Energies Alternatives

University of Illinois

New York University

Subhasish Mitra

Nishant P Patil

David Lin

Hai Lin

Binh Quang Le

Chung Chun Wan

Elisa Vianello

Pascal Vivet

Henri-Pierre Charles

Edward J McCluskey

H-s Philip Wong

Etienne Nowak

Deming Chen

Roman Gauchi

Fan Tony Wu

Keith Campbell

Philip Wong

Clark Barrett

Eshan Singh

The present description concerns a memory module () adapted to implementing computing operations, the module comprising a plurality of elementary blocks () arranged in an array according to rows and columns, wherein: each elementary block () comprises a memory circuit () adapted to implementing computing operations, and a configurable transfer circuit (); each configurable transfer circuit () is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit () is connected to an input-output port () of the module; and the internal control circuit () is configured to read at least one instruction signal from the input-output port () of the module and accordingly parameterize the configuration of the configurable transfer circuits (), and define the size of the operand vectors of the computing operations.

Reconfigurable memory module designed to implement computing operations

The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Circuit and method for programming resistive memory cells

Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods&#x2014;which we call Quick Error Detection&#x2014;Hardware (QED-H)&#x2014;advantageously quickly detect and fix anomalies (bugs) within SoC hardware components&#x2014;and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.

System-level validation of systems-on-a-chip (SoC)

Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called 'change detectors' which introduce only a small area overhead. Symbolic QED exhibits: 1) A systematic (and automated) approach to inserting 'change detectors' during a design phase; 2) Quick Error Detection (QED) tests that detect bugs with short error detection latencies and high coverage; and 3) Formal techniques that enable bug localization and generation of minimal bug traces upon bug detection.

Post-silicon validation and debug using symbolic quick error detection

An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.

Apparatus for detecting bugs in logic-based processing devices

A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

System and method for testing a logic-based processing device

A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.

Multiple carbon nanotube transfer and its applications for making high-performance carbon nanotube field-effect transistor (CNFET), transparent electrodes, and three-dimensional integration of CNFETs

A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.

System and method for analyzing a nanotube logic circuit

A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.

Nanotube logic circuits

The present invention provides a word voter for redundant systems with n modules wherein each of these n modules generates a word output. The word voter receives word outputs from each of the n modules. A voter decision is generated by the word voter utilizing a word basis of the word output of each of the n modules. The voter is based on a majority voting principle. The advantage of the present invention is that the word voter can be used to design redundant systems, such as, but not limited to, TMR systems, that are protected against common mode and multiple output failures. In addition, another advantage of the present invention is that is provides for a technique to efficiently design a TMR simplex system. The present invention provides a word voter for hardware systems.

Growing community of inventors

Palo Alto, CA, United States of America

Subhasish Mitra