Axiowave Networks, Inc.

Subhasis Pal

Xiaolin Wang

Satish Soman

Benjamin Marshall

A novel scalable-port non-blocking shared-memory output-buffered variable length queued data switching method and apparatus wherein successive data in each of a plurality of queues of data traffic is distributed to corresponding cells of each of successive memory channels in striped fashion across a shared memory space.

Method of scalable non-blocking shared memory output-buffered switching of variable length data packets from pluralities of ports at full line rate, and apparatus therefor

A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor

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Hopkinton, MA, United States of America

Subhasis Pal