International Business Machines Corporation

Other

Subhash Balakrishna Kulkarni

Randy William Mann

Werner A Rausch

Dominic Joseph Schepis

Ronald Jay Bolam

Kevin K Chan

Bomy A Chen

Luigi Ternullo, Jr

Gangadhara Swami Mathad

Eric Adler

Rajiv M Ranade

Edward J Nowak

Francis Roger White

Terence B Hook

Jerome Brett Lasky

Michael R Poponiak

Arun K Gaind

Jerome Bret Lasky

A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.

Method to achieve increased trench depth, independent of CD as defined by lithography

The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.

Method to fill deep trench structures with void-free polysilicon or silicon

An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact&mdash;which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Silicon-on-insulator chip having an isolation barrier for reliability

Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability

An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact--which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

An improved field effect transistor (FET) structure is disclosed. It comprises a first insulator layer containing at least one primary level stud extending through the layer; an undoped cap oxide layer disposed over the insulator layer and abutting the upper region of each stud; a primary level thin film transistor (TFT) disposed over the undoped cap oxide layer; and a planarized oxide layer disposed over the TFT. Multiple TFT's can be stacked vertically, and connected to other levels of studs and metal interconnection layers. Another embodiment of the invention includes the use of a protective interfacial cap over the surface of tungsten-type studs. The FET structure can serve as a component of a static random access memory (SRAM) cell. Related processes are also disclosed.

Semiconductor structure incorporating thin film transistors, and methods

Improved field effect transistor (FET) structures are described. They include a thin film transistor (TFT), wherein a contact layer directly connects a diffusion region of the TFT to an active site of another device, e.g., another transistor. This invention is especially suitable for TFT's which are built on one or more conductive studs. Static random access memory (SRAM) cells incorporating one or more of the TFT's are also described. Moreover, this invention is directed to methods for preventing or alleviating the problems associated with gouging during formation of contact layers.

Field effect transistor having contact layer of transistor gate

Semiconductor structures which incorporate thin film transistors

Semiconductor structure incorporating thin film transistors with undoped

The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

Semiconductor manufacturing process for low dislocation defects

A reduced pressure epitaxial deposition method is disclosed to maximize performance and leakage limited yield of devices formed in the epitaxial layer. The method includes specified prebake and deposition conditions designed to minimize arsenic (buried subcollector) and boron (buried isolation) autodoping effects when pressures below one atmosphere are selected in accordance with the subcollector-to-isolation area ratio.

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Peekskill, NY, United States of America

Subhash Balakrishna Kulkarni