Vlsi Technology, Inc.

Philips Electronics North America Corporation

Koninklijke Philips Corporation N.v.

Broadcom Corporation

Philips Semiconductors Inc.

Zeevo, Inc.

Other

Philips Semiconductor, Inc.

Lsi Technology, Inc.

Subhas Bothra

Harlan Lee Sur, Jr

Milind Ganesh Weling

Calvin T Gabriel

Stephen L Skala

Xi-Wei Lin

Ling Q Qian

Rao Venkateswara Annapragada

Tom McKay

Carol Barrett

Dipankar Pramanik

Samit S Sengupta

Michael N Misheloff

Edward D Nowak

Martin Harold Manley

Satyendra S Sethi

Tammy D Zheng

Robert L Payne

Daniel C Baker

Jayarama N Shenoy

Paul R Findley

Victor C Liang

Dipu Pramanik

Emmanuel Demuizon

Jacob D Haskell

Ian Robert Harvey

Samuel Vance Dunton

Louis Pandula

David C Chapman

Donald D Baumann

Thomas G McKay

William K Shu

Wesley R Erck

Christopher S Olsen

Jay Patel

David Eatock

Ravi Jhota

Steven L Skala

Tekle M Tafari

Harold J Levy

An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

Fully differential, high Q, on-chip, impedance matching section

A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states 'fire,' 'police,', &#x201c;yelling,&#x201d; etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.

System and method allowing for safe use of a headset

Embodiments of the present invention provide a system and method with which to implement metal fill during design using tools such as a place and route tools or layout tools. Unlike prior known solutions where metal fill was performed after design and layout, performing metal fill during layout with a uniform pattern of conductive traces sized and spaced according to the design rules of the device to be fabricated resulting in more planning and design. Dividing the conductive traces into active and inactive segments during the design and layout identifies potentially negative impacts on critical or sensitive device elements within the device during design and layout. Previously, metal fill was implemented after design and layout and often resulted in negative impacts not previously accounted for during IC design. Embodiments of the present invention reduce degradation, seen in other devices where metal fill is incorporated after design and layout. Additionally, because the physical characteristics of inactive metal fill segments are considered during design and layout of the ICs.

Method to implement metal fill during integrated circuit design and layout

Embodiments of the present invention provide an integrated circuit (IC) in which power to input output (IO) drivers may be distributed within unused areas over macro processing circuits. This IC includes a long distance power and ground distribution network, an input output (IO) power and ground distribution network, a number of macro processing circuits, and IO circuits. The long distance power and ground distribution network electrically couples to the IO power and ground distribution network. Both the power and ground distribution networks may be located within the upper level conductive layers. IO power and ground distribution network locally supplies power and ground to IO circuits. Macro processing circuits may be located beneath the power distribution network as some macro processing circuits do not require access to upper level conductive layers. By placing these macro processing circuits beneath these power distribution networks, die size may be reduced.

I/O driver power distribution method for reducing silicon area

A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer. Furthermore, the present invention enables the operator of the CMP machine to know within a certain accuracy the film (e.g., dielectric layer) thickness remaining after the CMP process of the semiconductor wafer. Moreover, the present invention essentially eliminates excessive chemical mechanical polishing of the semiconductor wafer. As such, not as much dielectric material needs to be deposited on the wafer in order to compensate for excessive chemical mechanical polishing of the semiconductor wafer. Therefore, the present invention is able to reduce fabrication costs of semiconductor wafers.

Method of using films having optimized optical properties for chemical mechanical polishing endpoint detection

Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Pad metallization over active circuitry

Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7. In this manner, the tungsten plug will come in direct contact with the basic solution that causes the tungsten plug to be removed while the pressure transducer structure is submerged in the basic solution.

Semiconductor pressure transducer structures and methods for making the same

A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Semiconductor inductor and methods for making the same

A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure. Damascene processes are used to manufacture the multiple metal layer interconnections.

Structure to increase density of MIM capacitors between adjacent metal layers in an integrated circuit

Methods for making semiconductor inductor

A method of forming a co-axial interconnect line in a dielectric layer is provided. The method includes defining a trench in the dielectric layer and then forming a shield metallization layer within the trench. After forming the shield metallization layer, a conformal oxide layer is deposited within the shield metallization layer. A center conductor is then formed within the conformal oxide layer. Once the center conductor is formed, a fill oxide layer is deposited over the center conductor. A cap metallization layer is then formed over the fill oxide layer and is in contact with the shield metallization layer.

Methods for forming co-axial interconnect lines in a CMOS process for high speed applications

Growing community of inventors

San Jose, CA, United States of America

Subhas Bothra