Intel Corporation

Subhankar Panda

John G Holm

Gaurav Porwal

Theodros Yigzaw

Stalinselvaraj Jeyasingh

David A Locklear

Omar Avelar Suarez

Steven A Filary

Christopher J Stedman

Carlos Vallin

Kuljit Singh Bains

Rajat Agarwal

Yen Hsiang Chew

Sarathy Jayakumar

Kjersten E Criss

Rebecca Z Loop

Piotr Tylenda

Hugo Enrique Gonzalez Chavero

Satyaprakash Nanda

Guarav Porwal

Agnieszka Potulska

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

Adaptive internal error scrubbing and error handling

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to provide management of a connected hardware subsystem with respect to one or more of reliability, availability and serviceability, and coordinate the management of the connected hardware subsystem with respect to one or more of reliability, availability and serviceability between the connected hardware subsystem and a host. Other embodiments are disclosed and claimed.

Cloud scale server reliability management

Techniques and mechanisms for providing performance monitoring information. In an embodiment, a performance monitor circuit receives a communication which indicates a format comprising multiple fields which are each to store a respective count of monitored events. A programming of the performance monitor circuit, based on the communication, designates first bits and second bits of the register to provide, respectively, a first first field and a second field according to the format. Performance monitoring subsequent to the programming successively tallies a first count of first events which occur during a first period of time, and a second count of second events which occur during a second period of time. In another embodiment, performance monitoring results in the register concurrently storing both the first count and the second count.

Device, system, and method to concurrently store multiple PMON counts in a single register

Upon occurrence of multiple errors in a central processing unit (CPU) package, data indicating the errors is stored in machine check (MC) banks. A timestamp corresponding to each error is stored, the timestamp indicating a time of occurrence for each error. A machine check exception (MCE) handler is generated to address the errors based on the timestamps. The timestamps can be stored in the MC banks or in a utility box (U-box). The MCE handler can then address the errors based on order of occurrence, for example by determining that the first error in time causes the remaining error. The MCE can isolate hardware/software associated with the first error to recover from a failure. The MCE can report only the first error to the operating system (OS) or other error management software/hardware. The U-Box may also convert the timestamps into real time to support user debugging.

Serializing machine check exceptions for predictive failure analysis

Techniques and apparatus for remotely accessing debugging resources of a target system are described. A target system including physical compute resources, such as, processors and a chipset can be coupled to a controller remotely accessible over a network. The controller can be arranged to facilitate remote access to debug resources of the physical compute resources. The controller can be coupled to debug pin, such as, those of a debug port and arranged to assert control signals on the pins to access debug resources. The controller can also be arranged to exchange information elements with a remote debug host to include indication of debug operations and/or debug results.

Remote debug for scaled computing environments

An embodiment of a semiconductor package apparatus may include technology to create a range search tree based on a data stream, cluster data from the data stream based on the range search tree and application of a modified density based spatial cluster of applications with noise scheme, and detect an anomaly in the data stream based on the clustered data. Other embodiments are disclosed and claimed.

Autonomous anomaly detection and event triggering for data series

A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

Delayed error processing

An apparatus and method for machine check bank reporting in a processor. For example, one embodiment includes a processor comprising: one or more cores to execute instructions and process data; a plurality of machine check architecture banks to store errors detected during execution of the instructions; error monitoring circuitry to detect the errors and responsively update the MCA banks; and a first error register (FERR) into which a first error vector is to be stored to identify an MCA bank containing a first error in an error sequence, the error monitoring circuitry to update the first error vector responsive to detecting the first error; and one or more next error registers (NERRs) to store one or more error vectors to one or more other MCA banks containing subsequent errors occurring after the first error.

Apparatus and method for vectored machine check bank reporting

A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.

Disambiguation of error logging during system reset

Methods and systems to identify image pixels as edge pixels using fractal signatures associated with the image pixels. Fractal signatures may include one or more of a variety of fractal dimensions. A fractal dimension of a pixel may be generated from an array of pixels that include the pixel, from x and y coordinates and one or more of luminosity values and color values associated with pixels in the array of pixels. Pixels may be identified as edge pixels when their corresponding fractal signatures are equal to or greater than a fractal signature threshold. The fractal signature threshold may be generated in a supervised fashion.

Supervised edge detection using fractal signatures

Methods and apparatus for accessing a redundant array of independent drives (RAID) storage device are disclosed. In some embodiments file data is broken into multiple segments. A cryptographic operation is performed on one or more segments to generate encrypted segment(s). One or more parity syndrome is computed from the encrypted segment(s) and the unencrypted segment(s). The encrypted segment(s), the unencrypted segment(s) and the parity syndrome(s) are striped onto different individual drives. Since the cryptographic operation is not performed on all the segments, it may also be performed concurrently with computing of parity syndrome(s) from other unencrypted segments.

Growing community of inventors

Portland, OR, United States of America

Subhankar Panda