Intel Corporation

Subhajit Dasgupta

Abhishek R Appu

Prasoonkumar Surti

Srivallaba Mysore

Joydeep Ray

Vasanth Ranganathan

Michael J Norris

Travis T Schluessler

Linda L Hurd

Eric J Hoekstra

Daren J Schmidt

Hiroshi Akiba

Anujan Varma

Yoav Harel

Jaisimha Bannur

Daniel Johnston

Methods, systems and apparatuses may provide for hardware sampler technology that determines mip region dimensions of a feedback map based on a description of the feedback map, identifies accessed texels in a texture based on a view of a resource that is paired with the feedback map, and records the accessed texels in the feedback map based on the mip region dimensions.

Native sampler feedback technology

One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

Fragment compression for coarse pixel shading

One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

Dedicated fixed point blending for energy efficiency

One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.

Methods and apparatus relating to Multi-Sample Anti-Aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization are described. In an embodiment, Multi-Sample Anti-Aliasing (MSAA) logic generates render subspan plane information based on data stored in a cacheline. One or more read operations to memory are suppressed based on a determination that the cacheline is in a clear state. Other embodiments are also disclosed and claimed.

Multi-sample anti-aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization

In general, in one aspect, the disclosure describes an apparatus that includes a plurality of flow controllable queues containing data to be transmitted. The queues are organized by flow. The apparatus also includes a plurality of destinations to receive data from the plurality of queues. The apparatus further includes a controller to continually maintain an aggregate count of data ready for transmission to the destinations and determine next queue to transmit data from based at least partially on the aggregate counts.

Growing community of inventors

Bengaluru, India

Subhajit Dasgupta