Astera Labs, Inc.

Cisco Technology, Inc.

Asiera Labs, Inc.

Subbarao Arumilli

Enrique Musoll

Pulkit Khandelwal

Casey Morrison

Ken (Keqin) Han

Chi Feng

Jitendra Mohan

Vivek Trivedi

Charan Enugala

Vikas Khandelwal

Anh T Tran

Li Li

Dinesh Ganapathy Dutt

Sanjay Sane

Michael Brian Galles

Peter Clarke Newman

Pirabhu Raman

Mahesh Srinivasa Maddury

Lin Shen

Vijay Rangarajan

Ray Kloth

Prakash Appanna

A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Retimer with path-coordinated flow-rate compensation

A memory control component encodes over-capacity data into an error correction code generated for and stored in association with an application data block, inferentially recovering the over-capacity data during application data block read-back by comparing error syndromes generated in detection/correction operations for respective combinations of each possible value of the over-capacity data and the read-back application data block.

Capacity-expanding memory control component

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

Low-latency retimer with seamless clock switchover

A signaling-link retimer concatenates discontiguous leading and trailing portions of a precoded and scrambled symbol stream, shunting the trailing portion of the stream ahead of unneeded stream content to dynamically reduce the number of symbols queued between retimer input and output and thus reduce retimer transit latency.

Low-latency signaling-link retimer

A decoding engine within an integrated-circuit (IC) component iteratively executes error detection/correction operations with respect to a sequence of input data volumes to generate a corresponding sequence of error syndrome values, the input data volumes each including a first block of data and corresponding error correction code retrieved from one or more external memory components together with a respective one of a plurality of q-bit data patterns. Selector circuitry within the decoding engine selects one of the plurality of q-bit data patterns to be an output q-bit value according to error-count differentiation indicated by the error syndrome values.

A memory control device implements split storage of user-data and metadata components of a compound write data word, outputting the user-data component via a memory control interface for storage within an external memory subsystem while separately storing the metadata component within a metadata cache implemented within the memory control device.

Metadata-caching integrated circuit device

First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

Retimer with mesochronous intra-lane path controllers

Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Configurable-aggregation retimer with media-dedicated controllers

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Cupertino, CA, United States of America

Subbarao Arumilli