Synopsys, Inc.

Subarnarekha Sinha

Charles C Chiang

Qing Su

Zongwu Tang

Fan Yang

Jing Guo

Jingyu Xu

Daniel Zhang

Jianfeng Luo

Xuan Zeng

Hailong Yao

Kent Y Kwang

Jamil Kawa

Min-Chun Tsai

Hui-Ru Jiang

Yen-Ting Yu

Alex Miloslavsky

Kevin A Beaudette

Ya-Chung Chan

An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2&#xd7;-4&#xd7; computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.

Distance metric for accurate lithographic hotspot classification using radial and angular functions

An accurate process hotspot detection technique based on DRC is provided. In this technique, critical DRC rules can be extracted from a pattern. This extraction can include generating horizontal tiles and vertical tiles in the pattern, and adding directed edges to indicate relations between adjacent tiles in the pattern. Rule rectangles, which can also be generated during the critical DRC rule extraction, describe polygon placement in the pattern with a minimal number of critical DRC rules. The extracted DRC rules can be included in a DRC runset file. DRC can be performed with the DRC runset file on a layout. The DRC results can be filtered using the rule rectangles to identify potential hotspots and to verify actual hotspots.

Accurate process hotspot detection using critical design rule extraction

One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations for the constituent set of geometries wherein the perturbed pattern clip no longer causes a manufacturing hotspot. The system then extracts a set of correction guidance descriptions from the first range of variations for correcting the pattern clip. Subsequently, the system stores the pattern clip and the set of correction guidance descriptions in the pattern-clip-based hotspot database.

Pattern-clip-based hotspot database system for layout verification

One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.

Dual-purpose perturbation engine for automatically processing pattern-clip-based manufacturing hotspots

An dual function distance metric for pattern matching based hotspot clustering is described. The dual function distance metric can handle patterns containing multiple polygons, is easy to compute, and is tolerant of small variations or shifts of the shapes. Compared with an XOR distance metric pattern clustering, the dual function distance metric can achieve up to 37.5% accuracy improvement with 2X-4X computational cost in the context of cluster analysis. The dual function distance metric is reliable and accurate for characterizing clips (e.g. hotspots), thereby making it desirable for industry applications.

One embodiment of the present invention provides a system that identifies hotspot areas in a layout. The system receives the layout and a via range pattern which indicates one or more vias and performs range-pattern matching (RPM) on the layout based on a via-free range pattern derived from the via range pattern. The system further identifies at least one candidate area and determines whether via(s) in the candidate area matches the via(s) in the via range pattern. The system can also receives a range pattern with don't care regions. The system determines a core pattern from the range pattern, performs RPM based on the core pattern, and identifies a candidate area. The system then determines whether areas surrounding the candidate area match a non-core effective pattern of the range pattern. The system further determines if the areas surrounding the candidate area satisfy the constraints associated with any vias and the don't care regions.

Range pattern matching for hotspots containing vias and incompletely specified range patterns

A memory is encoded with a data structure that represents a pattern having a range for one or more dimensions and/or positions of line segments therein. The data structure identifies two or more line segments that are located at a boundary of the pattern. The data structure also includes at least one set of values that identify a maximum limit and a minimum limit (i.e. the range) between which relative location and/or dimension of an additional line segment of the pattern in a portion of a layout of an integrated circuit (IC) chip, represents a defect in the IC chip when fabricated. In most embodiments, multiple ranges are specified in such a range defining pattern for example a width range is specified for the width of a trace of material in the layout and a spacing range is specified for the separation distance between two adjacent traces in the layout.

Range pattern definition of susceptibility of layout regions to fabrication issues

A range pattern is matched to a block of an IC layout by slicing the layout block and the range pattern, followed by comparing a sequence of widths of layout slices to a sequence of width ranges of pattern slices and if the width of any layout slice falls outside the width range of a corresponding pattern slice then the layout block does not match the range pattern. If the comparison succeeds, further comparisons are made between a sequence of lengths of layout fragments in each layout slice and a sequence of length ranges of pattern fragments in corresponding pattern slices. If the length of any layout fragment falls outside the length range of a corresponding pattern fragment then the block does not match the range pattern. If all lengths are within their respective ranges, then the block matches the pattern, although additional constraints are checked in some embodiments.

Identifying layout regions susceptible to fabrication issues by using range patterns

Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.

Fast evaluation of average critical area for IC layouts

One embodiment of the present invention provides a system that identifies a substantially minimal set of phase conflicts in a PSM-layout that when corrected renders the layout phase-assignable. During operation, the system constructs a phase-conflict graph from a PSM-layout. Next, the system removes a first set of edges from the phase-conflict graph to make the graph planar, and then removes a second set of edges to make the graph bipartite. The system then adds zero or more edges of the first set of edges, and determines a set of phase conflicts in the PSM-layout based on the remaining edges in the first set of edges and the second set of edges. Next, the system identifies a set of lines in the layout, such that adding space along the set of lines results in a phase-assignable PSM-layout.

Method and apparatus for identifying and correcting phase conflicts

One embodiment of the present invention provides a system for facilitating floorplanning for three-dimensional integrated circuits (3D ICs). During operation, the system receives a number of circuit blocks. The system places the blocks in at least one layer of a multi-layer die structure and sets an initial value of a time-varying parameter. The system then iteratively perturbs the block arrangement until the time-varying parameter reaches a pre-determined value.

Method and system for facilitating floorplanning for 3D IC

One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.

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Menlo Park, CA, United States of America

Subarnarekha Sinha