Texas Instruments Corporation

Sualp Aras

Abidur Rahman

Md Abidur Rahman

Eung Jung Kim

Adam Quirk

Xiaochun Zhao

Vijay Krishnamurthy

Min Chu

Stephen Nortman

Kyle Clifton Schulmeyer

Guhaprakash Amudhan

Deric Wayne Waters

Roland Karl Son

Tatsuyuki Nihei

Tri Cao Nguyen

Ralph Braxton Wade, Iii

A bidirectional level shifter circuit includes first and second driver circuits, first and second comparators, and a control circuit. The first driver circuit includes a first driver output and a first enable input. The second driver circuit includes a second driver output and a second enable input. The first comparator includes a first comparator output, a first reference input, and a first comparator input that is coupled to the second driver output. The second comparator includes a second comparator output, a second reference input, and a second comparator input is coupled to the first driver output. The control circuit includes a first control input coupled to the first comparator output, a second control input coupled to the second comparator output, a first control output coupled to the first enable input, and a second control output coupled to the second enable input.

Level shifter with automatic direction sensing

A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Clamp for power transistor device

A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents is less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

Layout for reduced cross-talk in common terminal transistor

A circuit protective system. The system includes an output controlling enablement of a transistor and an input sensing an operational parameter associated with the transistor. The system also includes detection circuitry providing an event fault indicator if the operational parameter violates a condition. The system also includes protective circuitry disabling the transistor in response to the event fault indicator and subsequently selectively applying an enabling bias to the transistor; the enabling bias is selected from at least two different bias levels and in response to a number of event fault indications from the detection circuitry.

Method of achieving robustness of the device in short circuit condition by adjusting the current limit threshold based repetitive fault condition

Methods, apparatus, systems, and articles of manufacture providing adaptive voltage clamps are disclosed. An example apparatus includes a voltage clamp to clamp a drain-to-source voltage of a transistor to a first voltage when the drain-to-source voltage exceeds the first voltage, and a controller to generate a control signal to direct the voltage clamp to clamp the drain-to-source voltage to a second voltage different from the first voltage based on a fault signal.

Adaptive voltage clamps and related methods

A microelectronic device has a common terminal transistor with two or more channels, and sense transistors in corresponding areas of the channels. The channels and the sense transistors share a common node in a semiconductor substrate. The sense transistors are configured to provide sense currents that are representative of currents through the corresponding channels. The sense transistors are located so that a ratio of the channel currents to the corresponding sense currents have less than a target value of cross-talk. The microelectronic device may be implemented without a compensation circuit which provides a compensation signal used to adjust one or more of the sense currents to reduce cross-talk. A method of forming the microelectronic device, including estimating a potential distribution in the semiconductor substrate containing the common node of the common terminal transistor, and selecting locations for the sense transistors based on the estimated potential distribution, is disclosed.

State machine controlling power transistor through fault and no fault

In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.

Radio frequency detection circuit

A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.

Safe operating area energy limit system and method in power application

A circuit protective system. The system has: (i) an input for sensing an operational voltage responsive to a current flowing through a transistor; (ii) circuitry for applying a forced voltage at the input; (iii) voltage-to-current conversion circuitry for outputting a reference current in response to the forced voltage at the input; (iv) circuitry for providing a reference trim current in response to a trim indicator; and (v) comparison circuitry for outputting a limit signal in response to a comparison of the reference current and the reference trim current.

High current limit trim apparatus and methodology

A circuit reliability system with a first voltage supply for outputting a first voltage and a second voltage supply for outputting a second voltage. The system also includes: (i) at least one node for providing a potential in response to the first voltage and the second voltage; (ii) monitoring circuitry for detecting the first voltage exceeding a threshold; and (iii) disabling circuitry, for disabling the second voltage supply in response to the monitoring circuitry detecting the first voltage exceeding a threshold.

Circuit reliability improvement by detecting and mitigating high voltage transient event at supply

Protective circuit enabling different bias levels responsive to event faults

An apparatus includes a FET device having a drain terminal, source terminal and a gate terminal; a first supply voltage coupled to the drain terminal of the FET; an output terminal coupled to the source terminal of the FET; a bias current supply coupled to the gate terminal of the FET; a second supply voltage coupled to the gate terminal of the FET; a current sensing circuit coupled to output a sense current proportional to the current flowing through the FET; a current limit comparator coupled to the sense current and comparing the sense current to a predetermined limit current; a pull down current circuit coupled to remove current from the gate terminal of the FET; a current time derivative circuit coupled to the sense current and outputting a sense rate current; and a circuit coupled to receive the sense rate current and coupled to the bias current supply.

Methods and apparatus for continuous current limiting for FETS in high inductive load systems

A method for measuring for generating a touch capacitance measurement is provided. Gain and offset control signals are generated, where the gain and offset control signals are adjusted to compensate for base capacitance of a touch sensor. The gain control signal is applied to a touch sensor during a first phase of a clock signal, and the offset control signal is applied to an output circuit during a second phase of the clock signal. The output circuit is coupled to the touch sensor during the second phase of the clock signal. The touch capacitance measurement is generated by compensating for the base capacitance with the gain and offset control signals, and a gain is applied to the touch capacitance measurement.

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Dallas, TX, United States of America

Sualp Aras