Nepes Co., Ltd.

Su Yun Kim

Dong Hoon Oh

Yong Tae Kwon

Jun Kyu Lee

Ju Hyun Nam

Kyeong Rok Shin

Yong Woon Yeo

A semiconductor package includes a semiconductor chip including a chip pad, a first insulating layer provided on the semiconductor chip and including a first via hole, a first wiring pattern provided on the first insulating layer and connected to the chip pad through the first via hole of the first insulating layer, a second insulating layer provided on the first insulating layer and the first wiring pattern and including a second via hole, and a second wiring pattern provided on the second insulating layer and connected to the first wiring pattern through the second via hole of the second insulating layer, wherein the first insulating layer includes a first upper surface in contact with the second insulating layer and a first lower surface opposite to the first upper surface, and the first upper surface of the first insulating layer has surface roughness greater that the first lower surface of the first insulating layer.

Wafer-level design and wiring pattern for a semiconductor package

A semiconductor package includes an upper structure including a semiconductor chip and a first molding layer for molding the semiconductor chip, a lower structure provided on the upper structure, the lower structure including a conductive post and a second molding layer for molding the conductive post, and a redistribution structure provided between the upper structure and the lower structure, the redistribution structure including a wiring pattern for electrically connecting a pad of the semiconductor chip to the conductive post, in which a thermal expansion coefficient of the second molding layer is different from a thermal expansion coefficient of the first molding layer.

Semiconductor package comprising first molding layer and second molding layer with different thermal expansion coefficients

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.

Semiconductor package and manufacturing method thereof

A semiconductor package having improved impact resistance and excellent heat dissipation and electromagnetic wave shielding property, and a manufacturing method thereof are provided. There is provided a semiconductor package including: a chip having a contact pad provided on one surface thereof; a buffer layer formed on one surface of the chip; one or more wiring patterns disposed on the buffer layer, electrically connected to the contact pad of the chip, and extended to an outside of the chip; an external pad provided on the wiring pattern and electrically connected to the wiring pattern; an external connection terminal electrically connected to the external pad; and a mold layer formed to surround the other surface and a side surface of the chip and a side surface of the buffer layer, and formed up to the other surface of the wiring pattern.

Growing community of inventors

Cheongju-si, South Korea

Su Yun Kim