Samsung Electronics Co., Ltd.

Su-Yong Kim

Seungjae Lee

Il Han Park

Chi-Weon Yoon

Byung Soo Kim

Il-Han Park

Sang-Soo Park

Jong-Hoon Lee

Sang-Won Hwang

Sung-won Yun

Kang-Bin Lee

Jung-Yun Yun

Doogon Kim

Jung-Ho Song

Jae-Yun Lee

Jong-Yeol Park

Jinyub Lee

Ki-young Kim

Na-Young Choi

Mi-ra Eom

Ji-won Im

Sang-jin Hong

Joon Soo Kwon

A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

Memory device including a circuit for detecting word line defect and operating method thereof

A non-volatile memory device includes a first word line, a second word line, first memory cells, second memory cells, and an address decoder. The second word line is adjacent to the first word line. The first memory cells are connected to the first word line. The second memory cells are connected to the second word line. The second memory cells are connected to the first memory cells, respectively. The address decoder applies a first voltage to the first word line and applies a second voltage to the second word line in an over program period of the first memory cells. The first voltage is higher than a program voltage of the first and second memory cells. The second voltage is lower than a pass voltage of the first and second memory cells.

Non-volatile memory device and method of programming the same

To program in a nonvolatile memory device include a plurality of memory cells that are programmed into multiple states through at least two program steps, a primary program is performed from an erase level to a first target level with respect to the memory cells coupled to a selected word line A preprogram is performed from the erase level to a preprogram level in association with the primary program with respect to the memory cells coupled to the selected word line, where the preprogram level is larger than the erase level and smaller than the first target level A secondary program is performed from the preprogram level to a second target level with respect to the preprogrammed memory cells coupled to the selected word line.

Methods of programming multi-level cell nonvolatile memory devices and devices so operating

A nonvolatile memory device comprises multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines, an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address, a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address, a first line decoder configured to provide the second lines with wordline voltages needed for driving, and a voltage generator configured to generate the wordline voltages.

Nonvolatile memory device and related wordline driving method

A computing device including a display unit to display a screen, a touch input to receive a user's touch input on the display unit, and a controller to control the display unit to display at least a part of a plurality of user interface (UI) items on the screen with a predetermined degree of transparency, to scroll the UI items in a predetermined direction and to sequentially display the UI items on the screen according to the user's touch input, and to increase the degree of transparency of the UI items if the UI items are not scrolled any more.

Computing device and control method thereof

A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

Three dimensional semiconductor memory device

A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.

Nonvolatile memory device having stacked transistor configuration

Growing community of inventors

Yongin-si, South Korea

Su-Yong Kim