Intel Corporation

Su Wei Lim

Debendra Das Sharma

David J Harriman

Mahesh U Wagh

James E Jaussi

Mikal Hunsaker

Poh Thiam Teoh

Ting Lok Song

Ricardo E James

Hooi Kar Loo

Jennifer Chin

Joon Teik Hor

Bruce A Tennant

Say Cheong Gan

Sun Zheng E

Sujea Lim

Michelle C Jen

Kah Meng Yeem

Ming Yi Lim

Quinn Devine

Ronald W Swartz

Chai Huat Gan

Ngek Leong Guok

Siang Lin Tan

Dan Froelich

Ming Chew Lee

Venkatraman Iyer

Santosh Ghosh

Chee Hak Teh

Zuoguo Wu

Gerald S Pasdast

Ishwar Agarwal

Eng Hun Ooi

Lily Pao Looi

Darren L Abramson

Michael W Leddige

Daniel S Froelich

Mark S Birrittella

Vui Yong Liew

Rohit R Verma

Bryan L Spry

Reouven Elbaz

Ofer J Nathan

Choon Gun Por

Yick Yaw Ho

Yueming Jiang

Hui Shi

Lip Khoon Teh

Patrick Maloney

Shashitheren Kerisnan

Anoop Kumar Upadhyay

Gim Chong Lee

Athourina Gevergiz

Ngeok Kuan Wai

Mary Siaw See Yeoh

Li Len Lim

Akshay Pethe

In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

System, apparatus and method for synchronizing multiple virtual link states over a package interconnect

Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

Virtualized link states of multiple protocol layer package interconnects

Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

Hardware mechanisms for link encryption

An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Reduced pin count interface

Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

Method, apparatus, and system for power management on a CPU die via clock request messaging protocol

An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Integrated universal serial bus (USB) type-C switching

Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

System and method for power management

In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Dual bus standard switching bus controller

Various embodiments are generally directed to an apparatus, method and other techniques for determining when a communications port is in a first low power state, determining that a coupled device entered a low power state and enabling a second low power state based on the determination that the device has entered the low power state, the second low power state to use less power than the first low power state.

Techniques enabling low power states for a communications port

Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Techniques for inter-component communication based on a state of a chip select pin

Growing community of inventors

Klang, Malaysia

Su Wei Lim