Skhynix Inc.

Dongbu Hitek Co., Ltd.

Su Jin Lim

Min Hwan Moon

A memory controller performs an efficient error correction operation. The memory controller controls a memory device. The memory controller includes: an error corrector configured to perform one or more error correction operations to correct an error included in data read from the memory device during a read operation, the one or more error correction operations including a first error correction operation performed using a first read voltage determined based on a threshold voltage distribution obtained by assuming that a number of memory cells in an erase state is equal to a number of memory cells in a program state and a data controller in communication with the error corrector to receive first error correction data obtained from the first error correction operation and configured to store the first error correction data in the memory controller.

Memory controller and operating method thereof

A memory controller controls a memory device including a plurality of memory cells. The memory controller may include a workload determination circuit configured to determine a workload state indicating an operating pattern of the memory device based on optimal read voltages for reading the plurality of memory cells when a read operation performed on the memory cells fails; and an operating environment setting circuit configured to set an operating environment of the memory device based on the workload state.

Memory controller to set operating environment of memory device, method of operating the same and storage device including the same

A memory system may include: a memory device configured to perform one or more of data write, read and erase operations; and a controller configured to execute an error management command and control the operation of the memory device, wherein the error management command is configured to determine first data which is highly likely to cause a read fail, among data stored in the memory device, determine one or more second data which is used to generate predicted error parity, and generate the predicted error parity based on the determined first and second data, and wherein the memory device performs the write operation to store indexes of the first and second data and the predicted error parity, under control of the controller.

Predicted error correction apparatus, operation method thereof and memory system using the same

A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller includes an RAM in which a category table that categories with respect to LBAs are defined and a read voltage table that read voltages with respect to the categories are set are stored and a controller configured to, when a read request and an LBA to be read are received from a host apparatus, determine a category corresponding to the LBA with reference to the category table and perform a read operation on a read-requested memory cell of the nonvolatile memory device by applying a read voltage corresponding to the determined category to the memory cell with reference to the read voltage table.

Data storage device and operating method thereof

A vertical BJT which has a maximal current gain for a photodiode area. According to embodiments, since the BJT can be formed together with the photodiode, and collector current flows up and down based on the double base structure, the magnitude of the current may be increased.

Verticle BJT, manufacturing method thereof

Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area.

Varactor and method for manufacturing the same

Embodiments relate to a horizontal type bipolar junction transistor element (BJT) and a CMOS image sensor having the same to form a photodiode. In embodiments, the bipolar junction transistor as well as collector current may flow uniformly in a horizontal direction, which may increase the entire amount of current. In embodiments, large current gain may be obtained. In embodiments, a bipolar junction transistor element with various current gains can be manufactured.

Bipolar junction transistor and CMOS image sensor having the same

Embodiments relate to a vertical-type CMOS image sensor, a method of manufacturing the same, and a method of gettering the same, in which source and drain regions are expanded to improve grounding and gettering effects. In embodiments, the vertical-type CMOS image sensor may include a silicon substrate, a first photodiode formed in a prescribed part of the silicon substrate, a first epitaxial layer formed on the silicon substrate, a second photodiode formed on the first epitaxial layer to overlap the first photodiode, a second epitaxial layer formed on the first epitaxial layer, a third photodiode formed on the second epitaxial layer to overlap the second photodiode, and first to third grounded dummy moats formed by implanting impurities into uniform parts on the silicon substrate, the first epitaxial layer, and the second epitaxial layer.

Growing community of inventors

Gyeonggi-do, South Korea

Su Jin Lim