Samsung Electronics Co., Ltd.

Su-Jin Jung

Byeong-Chan Lee

Bon-Young Koo

Jin-bum Kim

Kwan-heum Lee

Seok-hoon Kim

Cho-eun Lee

Nam-Kyu Kim

Seok-Hoon Kim

Woo-bin Song

Chul Kyu Kim

Dong-Suk Shin

Young-Pil Kim

Hoi-Sung Chung

Min-Hee Choi

Yang Xu

Myung-gil Kang

Kang-Hun Moon

Sun-ghil Lee

Dong-Chan Suh

Yongwoo Jeon

Jin-yeong Joe

Tae-Ouk Kwon

Nam Kyu Kim

Hyun-ho Noh

Sang-Pil Lee

Jangje Park

Kwan-Heum Lee

Heung-Kyu Park

Cho-Eun Lee

Jin-Bum Kim

A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same

A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same

An electronic device is provided. The electronic device includes a housing including a window, configured to form a 1side of the electronic device, and a 2side of the electronic device directed in an opposite direction of the 1side of the electronic device, a circuit board between the 1side and the 2side of the electronic device, and including an input circuit configured to detect an input based on a change in a capacitance, a spacer between the window and the circuit board, and having at least one space formed on one side facing the circuit board, a contact electrically connected to the input circuit by being mounted to one side of the circuit board, and contained in the at least one space, and a conductive plate coupled to the spacer, and electrically connected to the contact through the at least one space.

Electronic device including input apparatus

Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

Semiconductor devices

Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

Semiconductor devices including a finFET

FinFET with a single contact to multiple fins bridged together to form a source/drain region of the transistor

Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Semiconductor devices having composite spacers containing different dielectric materials

Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin.

Semiconductor device having a stress film on a side surface of a fin

A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

Semiconductor device and method of fabricating the same

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Hwaseong-si, South Korea

Su-Jin Jung