Skhynix Inc.

Su-Jin Chae

Chi-Ho Kim

Jae-Geun Oh

Myoung-Sub Kim

Hyo-June Kim

Jae Geun Oh

Sung-Kyu Min

Hyun-Seok Kang

Min-Seon Kang

Dae-Gun Kang

Dae Gun Kang

Su-Yeon Lee

Deok Lae Ahn

Won Ki Joo

Hyun Seok Kang

This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document may include a substrate including a first portion in a first region and a second portion in a second region; a plurality of memory cells disposed over the first portion of the substrate; a first insulating layer extending over the second portion of the substrate and at least partially filling a space between adjacent ones of the plurality of memory cells; and a second insulating layer disposed over the first insulating layer. The first insulating layer has a dielectric constant smaller than that of the second insulating layer, a thermal conductivity smaller than that of the second insulating layer, or both.

Electronic device and method for fabricating the same

A memory device and an electronic device including the same are provided. The memory device includes a first memory cell disposed at an intersection of first and second conductive lines that extend in first and second directions, respectively, a second memory cell spaced apart from the first memory cell by a first distance in the first direction, a third memory cell spaced apart from the first memory cell by a second distance in the second direction, a first insulating pattern disposed between the first memory cell and the second memory cell, and a second insulating pattern disposed between the first memory cell and the third memory cell. The second insulating pattern has a lower thermal conductivity than the first insulating pattern.

Memory device and electronic device including insulating patterns with different thermal conductivities

An electronic device may include a semiconductor memory, and the semiconductor memory may include a plurality of memory cells each including a variable resistance layer; a substituted dielectric layer filling a space between the plurality of memory cells; and an unsubstituted dielectric layer disposed adjacent to the variable resistance layer of each of the plurality of memory cells, wherein the unsubstituted dielectric layer may include a flowable dielectric material.

Growing community of inventors

Icheon, South Korea

Su-Jin Chae