Skhynix Inc.

Hynix Semiconductor Inc.

Semes Co., Ltd.

Su Jin Chae

Young Ho Lee

Jun Kwan Kim

Kang Sik Choi

Jin Ha Kim

Jin Hyock Kim

Young Seok Kwon

Yong Seok Eun

Sang Hyun Son

Ho Jin Cho

Eun Ah Lee

Keum Bum Lee

Min-Yong Lee

Hye Jin Seo

Dong Ok Ahn

Jun Soo Chang

Yong Jun Seo

Keum-Bum Lee

Young Dae Kim

Heon-Yong Chang

A temperature measuring apparatus with improved accuracy is provided. The temperature measuring apparatus comprises a test substrate having a thermal conductivity, a circuit board layer laminated on the test substrate and including a plurality of through holes exposing a top surface of the test substrate, bonding agent disposed in the plurality of through holes and having a thermal conductivity, and a plurality of sensors disposed on the bonding agent and for measuring a temperature.

Apparatus for temperature measurement and method of processing substrate

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

3D semiconductor integrated circuit device and method of manufacturing the same

A fabrication method of a resistance variable memory apparatus includes forming an amorphous phase-change material layer on a semiconductor substrate in which a bottom structure is formed, and performing crystallization on the amorphous phase-change material layer through a low-temperature plasma treatment process.

Fabrication method of resistance variable memory apparatus

A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Fabrication method of phase change memory device having self-aligned bottom electrode

Phase change memory device having self-aligned bottom electrode and fabrication method thereof

The manufacturing of a phase change memory device that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact. The formed bottom electrode contact exposes a switching device on a semiconductor substrate which the switching device is formed in, forming an insulating layer on a resultant structure of the semiconductor substrate including the bottom electrode contact by using an insulating compound having materials with different atomic sizes, and forming an insulating spacer within the bottom electrode contact hole by selectively etching the insulating layer.

Phase change memory device and fabrication method thereof

A phase change memory device and a method for manufacturing the same. The method includes the steps of defining bottom electrode contact holes by removing portions of an insulation layer, to expose bottom electrodes, on a semiconductor substrate on which the bottom electrodes and the insulation layer are sequentially formed; forming amorphous silicon spacers on inner sidewalls of the bottom electrode contact holes; and forming bottom electrode contacts in the bottom electrode contact holes.

Phase change memory device and method for manufacturing the same

A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming AlOand HfOdielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the AlOand HfOdielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.

Method for manufacturing capacitor of semiconductor element

Growing community of inventors

Gyeonggi-do, South Korea

Su Jin Chae