Samsung Electronics Co., Ltd.

Su-Hun Lim

Jung-Chak Ahn

Tae-Chan Kim

Seog-Heon Ham

Tetsuo Asaba

Yong-in Han

Myoung-Su Lee

Jin-Kyeong Heo

An apparatus for canceling a fixed pattern noise in a CMOS image sensor includes a storage device, a fixed pattern noise operation circuit, and a fixed pattern noise canceling circuit. The storage device stores first reference fixed pattern noises operated in a vertical blank section of an (n&#x2212;1)th frame. The fixed pattern noise operation circuit calculates second reference fixed pattern noises based on the first reference fixed pattern noises stored in the storage device and blank fixed pattern noises output in a vertical blank section of an n-th frame and outputs the second reference fixed pattern noises to the storage device to update the first reference fixed pattern noises to the second reference fixed pattern noises. The fixed pattern noise canceling circuit cancels active fixed pattern noises in combination signals based on the combination signals output in an active section of an (n+1)th frame and including the active fixed pattern noises and pixel signals and the second reference fixed pattern noises output from the storage device.

Method and apparatus for canceling fixed pattern noise in CMOS image sensor

An image-sensing device includes a driver and an array of pixels. The driver controls the array of pixels to output a combined image signal that is a combination of at least two image signals for at least two aligned pixels in at least two rows, for reducing vertical resolution in the sub-sampling mode. In addition, a mixing circuit further averages the resulting combined signals for M consecutive odd or even columns for reducing horizontal resolution in the sub-sampling mode.

Sub-sampling with higher display quality in image-sensing device

Provided are a solid state image sensing device and method for sub-sampling using inter-column analog domain signal summation, where, in the solid state image sensing device, a CDS unit receives reset signals from neighboring columns of the same color in an APS array, receives video signals from pixels generating the reset signals, and generates modulation signals respectively corresponding to the differences between the reset signals and the video signals, the modulation signals are activated according to activation of the previous modulation signals, and a digital signal output circuit generates a corresponding digital signal based on the final modulation signal corresponding to the sum of inter-column analog video signals among the modulation signals.

Solid state image sensing device and method for subsampling using inter-column analog domain signal summation

Provided are a CMOS image sensor (CIS) type image sensing device for averaging and sub-sampling analog image signals at a variable sub-sampling rate and a method of driving the same. The image sensing device includes: a two-dimensional active pixel sensor (APS) array including pixels arranged in rows and columns; an averaging unit averages reset signals and image signals alternately generated from each of pixels corresponding to odd- numbered and even-numbered rows and columns in based on a predetermined sub-sampling rate in a sub-sampling mode by repeating a method of accumulating, averaging, (and dumping) the reset signals and the image signals, and generating a comparison signal corresponding to a difference between the average of the reset signals and the average of the image signals; and a conventional digital signal output circuit that generates digital signals corresponding to the sub-sampled (averaged) image signals generated from the pixels represented by the comparison signal. The CIS type image sensing device can analog-average image signals output from pixels at a variable sub-sampling rate and carry out a sub-sampling operations for moving pictures, without increasing chip size.

Solid state image sensing device for analog-averaging and sub-sampling of image signals at a variable sub-sampling rate and method of driving the same

Provided are a CIS circuit that does not increase an initial voltage charge time allocated by a CDS even if a pixel size is reduced and a method of providing an initial charge to the CIS circuit. The CIS circuit may include an APS block, a current source block and a charge supply block. The APS block may output APS signals from APS output terminals in response to sensed image transfer signals, pixel select signals and pixel reset signals. The current source block may control currents flowing from the APS output terminals to a power supply in response to a bias voltage. The charge supply block may provide a quantity of charges to the APS output terminals in response to a representative reset signal and a pre-resent signal.

CMOS image sensor circuit and method of supplying initial charge thereof

A solid-state image-sensing device includes a pixel array and an averaging unit. The pixel array includes a matrix of pixels and includes a respective output line for each of a plurality of pixel groupings such as for each column of pixels. The averaging unit receives respective signals from first and second output lines of the pixel array to generate a pulse width signal that indicates an average of such respective signals. A respective signal of the first output line is generated from combining photocurrents from a first set of at least two pixels sensing a same first color in the pixel array.

Driving an image sensor with reduced area and high image quality

A correlated double sampling (CDS) amplifier for an image sensing device includes a plurality of capacitors and a switching network coupled to the plurality of capacitors and to a pixel of the image sensing device. The switching network is configured to couple the capacitors in parallel as an initial CDS difference voltage is generated, and then is configured to couple the capacitors in series for generating a final CDS difference voltage that is a multiple of the initial CDS difference voltage.

Correlated-double-sampling (CDS) with amplification in image sensing device

A column analog-to-digital conversion apparatus includes a first correlated double sampling (CDS) and comparison unit of a CDS and comparison circuit for generating a first comparison result signal in response to a first pixel output signal and a ramp signal, a second CDS and comparison unit of the CDS and comparison circuit for generating a second comparison result signal in response to the first pixel output signal and the ramp signal in a sub-sampling mode, and a data buffer for determining a code value of a most significant bit (MSB) based on the second comparison result signal, determining code values of remaining lower bits based on a counting value outputted from a counter, and generating a digital code including the MSB and the remaining lower bits.

Column analog-to-digital conversion apparatus and method supporting a high frame rate in a sub-sampling mode

A column analog-to-digital (ADC) circuit for preventing a sun black effect in a CMOS image sensor (CIS) is provided. The ADC circuit includes: a comparator having a signal voltage input port and a reference voltage input port, comparing a reset voltage output from one of a plurality of CIS pixels with a reference voltage in a reset sampling period, and outputting an overflow sensing signal when the reset voltage is lower than the reference voltage; and a digital converter converting the output of the comparator into digital data, wherein the digital converter comprises a first latch storing the overflow sensing signal and outputting a flag signal indicating an overflow in response to the overflow sensing signal in a signal sampling period, when the overflow sensing signal is output from the comparator in a first portion of the reset sampling period.

Column analog-to-digital converter of a CMOS image sensor for preventing a sun black effect

A ramp signal generation circuit is disclosed. The ramp signal generation circuit comprises a ramp signal generator, a buffer, a comparator, and a switching circuit. The switching circuit provides current to an output of the ramp signal generation circuit in response to a control signal output by the comparator. When a high slew rate is required, the output of the ramp signal generation circuit is driven by the current provided by the switching circuit. Otherwise, the output of the ramp signal generation circuit is driven by an output of the buffer.

Growing community of inventors

Suwon-si, South Korea

Su-Hun Lim