Taiwan Semiconductor Manufacturing Comp. Ltd.

Su-Hao Liu

Huicheng Chang

Liang-Yin Chen

Kuo-Ju Chen

Yee-Chia Yeo

Meng-Han Chou

Ying-Lang Wang

Lun-Kuang Tan

Tsan-Chun Wang

Li-Ting Wang

Chia-Cheng Chen

Wen-Yen Chen

Chun-Hung Wu

Chun Hsiung Tsai

Ziwei Fang

Jing-Huei Huang

Wei-Ming You

Syun-Ming Jang Jang

Kei-Wei Chen

Chih-Wei Chang

Huai-Tei Yang

Chien-Tai Chan

Yan-Ming Tsai

Chung-Ting Wei

Chien-Hao Chen

Chang-Miao Liu

Li-Chieh Wu

Kuo-Hsiu Wei

Ting-Kui Chang

Tang-Kuei Chang

Chia Hsuan Lee

Jie-Huang Huang

Tze-Liang Lee

Chun-Hsien Huang

Kai-Hsuan Lee

King-Yuen Wong

Jr-Hung Li

Chien-Chang Su

I-Hsieh Wong

Cheng-Yu Yang

Tsai-Jung Ho

Wei-Ting Chien

Pei-Yu Chou

Tien-Shun Chang

Tung-Po Hsieh

Tzu-Yang Ho

Shih-Hsiang Chiu

Hong-Chih Liu

Szu-Ying Chen

Tsz-Mei Kwok

Chien-Hung Lin

Wei-Yip Loh

Hung-Hsu Chen

Kuan-Yu Yeh

Tz-Shian Chen

Cheng-Jung Sung

Yi-Syuan Siao

Li-Heng Chen

Chii-Ming M Wu

Chih-Hung Chen

Hui-Chi Huang

Zi-Wei Fang

Chun-Hao Kung

Kao-Feng Liao

Sheng-Wen Yu

Ker-Hsun Liao

Wei-Ting Chang

Chia-Ling Chung

Chien-hao Chen

Wei-Han Huang

Yu-Kang Liu

Chun-Yi Chang

Ming-Feng Lin

Chii-Meng Wu

Chun Hsiang Tsai

Shun-Wu Lin

Chang-Maio Liu

A method of forming a semiconductor device includes forming a first dummy gate structure over a first region of a substrate and a second dummy gate structure over a second region of the substrate, the first region and the second region of the substrate having a first composition, the first composition having a first etch rate; implanting the first region of the substrate with dopants laterally adjacent to the first dummy gate structure, wherein after the implanting the first region, the first region has a second composition having a second etch rate, the second etch rate being different from the first etch rate; etching a first recess in the first region of the substrate having the second composition and a second recess in the second region having the first composition; and epitaxially growing a first source/drain region in the first recess and a second source/drain region in the second recess.

Semiconductor device and methods of forming the same

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Device having an air gap adjacent to a contact plug and covered by a doped dielectric layer

In an embodiment, a device includes: a source/drain region adjacent a channel region; an inter-layer dielectric on the source/drain region; a source/drain contact extending through the inter-layer dielectric and into the source/drain region; a metal-semiconductor alloy region between the source/drain contact and the source/drain region, the metal-semiconductor alloy region disposed beneath a top surface of the channel region, the metal-semiconductor alloy region including a first dopant; and a contact spacer around the source/drain contact, the contact spacer including the first dopant and an amorphizing impurity.

Transistor source/drain contacts and methods of forming the same

A method includes forming a fin structure over a substrate; depositing a dummy gate layer over the substrate and the fin structure; depositing a hard mask stack over the dummy gate layer; depositing a photoresist bottom layer over the hard mask stack, wherein the photoresist bottom layer has a first stress; performing an implantation process to the photoresist bottom layer to form an implanted bottom layer with a second stress closer to 0 than the first stress; patterning the implanted bottom layer; patterning the hard mask stack and the dummy gate layer by using the patterned implanted bottom layer as an etch mask to form a dummy gate structure over the fin structure; and replacing the dummy gate structure with a metal gate structure.

Method for manufacturing semiconductor device

A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.

Method for ion implantation uniformity control

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a gate structure, a dielectric structure and a contact structure. The substrate has source/drain (S/D) regions. The gate structure is on the substrate and between the S/D regions. The dielectric structure covers the gate structure. The contact structure penetrates through the dielectric structure to connect to the S/D region. A lower portion of a sidewall of the contact structure is spaced apart from the dielectric structure by an air gap therebetween, while an upper portion of the sidewall of the contact structure is in contact with the dielectric structure.

Methods of forming semiconductor device

A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.

Semiconductor devices including backside power rails and methods of manufacture

The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

Deposition window enlargement

Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Metal layer protection during wet etching

Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Semiconductor devices and methods of manufacture

Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

Semiconductor device and method

A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

Sacrificial layer for semiconductor process

A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

Contact formation with reduced dopant loss and increased dimensions

A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.

Bottom lateral expansion of contact plugs through implantation

In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.

Transistor contacts and methods of forming the same

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Jhongpu, Taiwan

Su-Hao Liu