Samsung Electronics Co., Ltd.

Su-Chul Kim

Hak-Soo Yu

Jong-Cheol Lee

Uk-Rae Cho

Hee-Choul Park

Kwang-Jin Lee

Uk-rae Cho

Min-Chul Chung

Hyun-Geun Byun

Kwon-il Sohn

Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.

Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode

Integrated circuit chips include an internal circuit including interconnected semiconductor devices that are configured to provide integrated circuit functionality, and a Test Element Group (TEG) circuit that is configured to allow measuring of electrical characteristics of the semiconductor devices. By providing a TEG circuit in the same integrated circuit chip as the internal circuit, the TEG circuit may accurately represent the electrical characteristics of the interconnected semiconductor devices of the internal circuit of the associated integrated circuit chip. The integrated circuit chip may be coupled to a test apparatus. The test apparatus includes a test probe that is configured to simultaneously contact the internal circuit and the TEG circuit. The test apparatus also can simultaneously test the integrated circuit functionality of the internal circuit, and measure the electrical characteristics of the semiconductor devices via the TEG circuit.

Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same

A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips

Memory architecture permitting selection of storage density after fabrication of active circuitry

Disclosed herein is a semiconductor memory device which comprises a decoding block, an OR gate and first and second precharge circuits. The decoding block generates section word line select signals and column select signals in response to a block select signal and row and column pre-decoder signals. And, the OR gate mixes the section word line select signals to generate a precharge signal. This forces the first precharge circuit to be activated or inactivated in synchronization with the section word line select signals. Furthermore, the second precharge circuit is activated or inactivated in synchronization with the column select signals. According to the precharge scheme of the present invention, there is prevented the period of the inactivation (activation) of the top and bottom precharge signals from being overlapped with the period of the activation (inactivation) of the section word line. As a result, the semiconductor memory device has an improved access speed.

Semiconductor memory with auto-tracking bit line precharge scheme

A synchronous memory comprises a memory cell array having a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals. The memory includes a first register circuit for storing a plurality of input data bits in response to the internal clock signal and to the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array, an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.

Data transmission circuitry of a synchronous semiconductor memory device

A synchronous burst semiconductor memory device with a pipelined multi-bit prefetch architecture includes separate internal address generators for respective read and write burst modes. The synchronous memory device also adopts an auto-tracking bit line scheme to reduce core cycle time, a shortened main data line for current reduction, a noise immune circuit having high-speed transfer characteristics through a dual-rail reset dynamic circuit, and strobe clocks synchronized with the output data to guarantee processor data-validation time.

Synchronous burst semiconductor memory device

A synchronous memory comprising: a memory cell array being comprised of a plurality of memory cells; a clock control circuit for receiving a first clock signal, a second clock signal, and a third clock signal, and for generating an internal clock signal, a plurality of control signals, and a plurality of flag signals; a first register circuit for storing a plurality of input data bits in response to the internal clock signal and the control signals; a second register circuit for storing the flag signals in response to the internal clock signal and the control signals; a write drive circuit for writing the input data bits passing through the first register circuit into the memory cell array in response to the flag signals during a write cycle; a sense amplifier circuit coupled to the memory cell array; an address comparator circuit for receiving read and write address signals and for generating a first, a second, and a third combination signals; and a switching circuit for transferring the input data bits passing through the first register circuit and the flag signals passing through the second register circuit to output terminals of the device.

A synchronous burst semiconductor memory device operating in synchronism with at least one external clock signal and capable of accessing data on every edge of the external clock signal is provided. The burst memory device includes a clock generator for generating a number of data output/input strobe clock signals synchronized with the external clock signal in response to a plurality of input information signals, and a data-out/in buffer for outputting/inputting internal/external data in synchronism with the data output/input strobe clock signals.

Growing community of inventors

Seoul, South Korea

Su-Chul Kim