Macronix International Co., Ltd.

Su-Chueh Lo

Chun-Hsiung Hung

Kuen-Long Chang

Ken-Hui Chen

Yi-Fan Chang

Nai-Ping Kuo

Han-Sung Chen

Yung-Feng Lin

Shang-Chi Yang

Ming-Chih Hsieh

Chia-Feng Cheng

Chin-Hung Chang

Chun-Yu Liao

Yu-Chen Wang

Wen-Pin Tsai

Wei-Yi Cheng

Cheng Ming Yih

Ken Hui Chen

Chia-Jung Chen

Kuen Long Chang

Shou Wei Huang

Kuo Yu Liao

Jian Shing Liu

Ta Kang Chu

Chu Ching Wu

Tai-Feng Chen

Hang-Ting Lue

Teng-Hao Yeh

Chun Hsiung Hung

Chi-Ling Chu

Chien-Hsin Liu

Wu-Chin Peng

Jian-Syu Lin

Jhen-Sheng Chih

Jeng-Kuan Lin

Chen-Chia Fan

Cheng-Ming Yi

Wenming Hsu

Tzu-Ting Chiu

A calibration apparatus of a memory device and a calibration method thereof are provided. The memory device is a 3D NAND flash with high capacity and high performance. The calibration apparatus includes an impedance, a strong-arm comparator, a logic circuit, and a calibration controller. The impedance is configured to generate a comparison voltage. The strong-arm comparator includes a differential input pair and a latch. The differential input pair compares a reference voltage and the comparison voltage to produce a comparison result. The latch latches the comparison result and generates a latch signal and an inverted latch signal accordingly. The logic circuit generates a comparison result signal according to the latch signal and the inverted latch signal. The calibration controller implements an impedance calibration in the memory device according to the comparison result signal.

Calibration apparatus and calibration method of memory device with strong-arm comparator

A duty cycle correction method and a duty cycle correction apparatus, adapted for correcting a duty cycle of a clock signal by using a duty cycle adjuster in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, the duty cycle is adjusted and input to data pads to generate data signals, wherein the data pads are divided into at least two groups and defined by data patterns that are inverse to each other; DC voltages of the data signals of a first group of data pads are detected to generate a first average DC voltage, and DC voltages of the data signals of a second group of data pads are detected to generate a second average DC voltage, the aforementioned average DC voltages are compared, and the duty cycle adjuster is controlled to adjust the duty cycle of the clock signal.

Duty cycle correction method and duty cycle correction apparatus

A data serializer, a latch data device using the same and a controlling method thereof are provided. The data serializer includes at least one data buffer and a de-skew buffer. The data buffer at least receives an inputting data and a controlling signal. An outputting signal and a complementary outputting signal, which is complementary to the outputting signal, are formed when the controlling signal is at a predetermined level. The de-skew buffer receives the complementary outputting signal to accelerate or slow down forming the outputting signal.

Data serializer, latch data device using the same and controlling method thereof

A duty cycle correction method and a duty cycle correction system, adapted for correcting a duty cycle of a clock signal by using a duty cycle corrector (DCC) in a high-capacity and high-performance semiconductor product such as a 3D NAND flash, are provided. In the method, training is performed on the DCC to correct the clock signal, and a training result is recorded after the training is finished; and the DCC is updated by the recorded training result before a next toggle of the clock signal.

Duty cycle correction method and duty cycle correction system

Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Managing data transfers in semiconductor devices by separating circuits for lower-speed-type data and higher-speed-type data

Systems, methods, circuits, and apparatus for managing signal transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: one or more target units each configured to receive a signal and a plurality of inverting units arranged on signal paths to the one or more target units. For each of the one or more target units, one or more corresponding inverting units of the plurality of inverting units are configured to invert the signal multiple times along a corresponding signal path to the target unit to cause a signal width of the inverted signal received by the target unit to be substantially identical to a signal width of the signal.

Managing signal transfers in semiconductor devices

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. In one aspect, a chiplet system includes multiple integrated circuit devices electrically connected together. The integrated circuit devices include an integrated circuit device including: an integrated circuit, a plurality of first type bonding pads electrically connected to the integrated circuit and electrically connected to at least one other of the integrated circuit devices, and one or more second type bonding pads electrically isolated from the at least one other of the integrated circuit devices. At least one of the plurality of first type bonding pads is configured to be electrically connected to a corresponding one of the one or more second type bonding pads.

Testing bonding pads for chiplet systems

Disclosed is a semiconductor device that has a first layer including conductive material, a bond wire coupled to an upper surface of the first layer, and a second layer including conductive material underneath the first layer. One or more interconnects couple the second layer to the first layer. In an example, the second layer has a plurality of discontinuous sections that includes (i) a connected section coupled to the one or more interconnects and (ii) one or more floating sections that are at least in part surrounded by the connected section, where the one or more floating sections are electrically floating and isolated from the connected section. The semiconductor device also includes an under-pad circuit on a substrate underneath the second layer, the under-pad circuit to transmit signals to one or more components external to the semiconductor device though the first layer.

Bond pad layout including floating conductive sections

Systems, methods, circuits, and apparatus including computer-readable mediums for testing bonding pads in multi-die packages, e.g., chiplet systems. An example integrated circuit device includes an integrated circuit, first type bonding pads and second type bonding pads. Each of the first type bonding pads is electrically connected to the integrated circuit and configured to be electrically connected to a corresponding external integrated circuit device. Each of the second type bonding pads is configured to have no electrical connection with the corresponding external integrated circuit device. Each of the first type bonding pads is configured to be electrically connected to a corresponding one of the second type bonding pads. A number of the first type bonding pads can be larger than a number of the second type bonding pads. Each of the second type bonding pads can have a larger pad area for probing than each of the first type bonding pads.

A memory apparatus and a control method are provided. The memory apparatus includes a non-volatile memory array having plural memory groups, and the control method is applied to the non-volatile memory array. The memory groups jointly share a first well, and the control method is applied to the non-volatile memory array. A first memory group among the memory groups is erased according to a first erase command after the memory apparatus is power-on, and a first amount of the memory groups are recovered in a first erase-recover procedure after the first memory group is erased. A second memory group among the memory groups is erased according to a second erase command after the first erase-recover procedure, and a second amount of the memory groups are recovered in a second erase-recover procedure after the second memory group is erased. The first amount is greater than the second amount.

Memory apparatus and associated control method for reducing erase disturb of non-volatile memory

A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.

Method and system for enhanced multi-address read operations in low pin count interfaces

A memory device and an operation method thereof are provided. The memory device comprises: a memory array; a decoding circuit coupled to the memory array, the decoding circuit including a plurality of first transistors, a plurality of second transistors and a plurality of inverters, the first transistors and the second transistors are paired; and a controller coupled to the decoding circuit, wherein the paired first transistors and the paired second transistors are respectively coupled to a corresponding one inverter among the inverters, and respectively coupled to a corresponding one among a plurality of local bit lines or a corresponding one among a plurality of local source lines; the first transistors are coupled to a global bit line; and the second transistors are coupled to a global source line.

Memory device and operation method thereof

A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.

Method and system for enhanced read performance in low pin count interface

A multi-die memory apparatus and identification method thereof are provided. The identification method includes: sending an identification initial command and a first start command to a plurality of memory devices by a controller for starting a first identification period; respectively generating a plurality of first target numbers by the memory devices; respectively performing first counting actions and comparing a plurality of first counting numbers with the first target numbers by a plurality of un-identified memory devices to set a first time-up memory device of the memory devices; and, setting an identification code of the first time-up memory device of the un-identified memory devices to be a first value.

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Hsinchu, Taiwan

Su-Chueh Lo