International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Samsung Electronics Co., Ltd.

Stmicroelectronics Gmbh

Su Chen Fan

Ruilong Xie

David V Horak

Andre P Labonte

Lars W Liebmann

Yann Mignot

Sivananda K Kanakasabapathy

Hsueh-Chung Chen

Heng Wu

Sanjay C Mehta

Tenko Yamashita

Junli Wang

Chih-Chao Yang

Christopher Joseph Waskiewicz

Huimei Zhou

Nicolas J Loubet

Shogo Mochizuki

Brent A Anderson

Peng Xu

Hemanth Jagannathan

Injo Ok

Indira P Seshadri

Shom Ponoth

Balasubramanian Pranatharthiharan

Ekmini Anuja De Silva

Huai Huang

Kangguo Cheng

Lawrence Alfred Clevenger

Chanro Park

Zuoguang Liu

Kisik Choi

Steven J Bentley

Takashi Ando

Veeraraghavan S Basker

Charles W Koburger, Iii

Terence B Hook

Julien Frougier

Andrew Mark Greene

Koichi Motoyama

Eric R Miller

Muthumanickam Sankarapandian

Johnathan E Faltermeier

Yongan Xu

James John Kelly

William James Taylor, Jr

Wei Wang

Jeffrey C Shearer

Balasubramanian S Pranatharthi Haran

Sukwon Hong

Pranatharthiharan Haran Balasubramanian

Min Gyu Sung

Ravikumar Ramachandran

Robert C Wong

Balasubramanian S Haran

Rajasekhar Venigalla

Cornelius Brown Peethala

Stuart A Sieg

Vimal Kumar Kamineni

Raghuveer Reddy Patlolla

Jay William Strane

Albert M Young

Tao Li

Miaomiao Wang

Jing Guo

Tsung-Sheng Kang

Ardasheir Rahman

Puneet Harischandra Suvarna

Hari Prasad Amanapu

Alexander Reznicek

Bruce Bennett Doris

Carl John Radens

Theodorus E Standaert

Xin Miao

Chun-chen Yeh

Oleg Gluschenkov

Dechao Guo

Ajey Poovannummoottil Jacob

Ruqiang Bao

Fee Li Lie

Jingyun Zhang

Xiuyu Cai

Chi-Chun Liu

Kafai Lai

David Lee Rath

Richard Anthony Conti

Pierre Morin

Cheng Chi

Murat Kerem Akarvardar

Chiahsun Tseng

Mark V Raymond

Catherine B Labelle

Adra Carr

Linus Jang

Kisup Chung

Gangadhara Raja Muthinti

Victor W C Chan

Jason Cantone

Mary Claire Silvestre

Sylvie M Mignot

Alex Joseph Varghese

A microelectronic structure including a stacked transistor having a lower transistor and an upper transistor. A shared contact in contact with a lower source/drain of the first lower transistor and an upper source/drain of the upper transistor. The shared contact includes a silicide layer, a metal plug layer, and a conductive metal layer.

Method and structure of forming sidewall contact for stacked FET

An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

Electronic devices with a low dielectric constant

A method is presented for constructing a semiconductor device. The method includes forming a plurality of fins over a nanosheet stack and a substrate, forming spacers between the nanosheet stack and one or more of the plurality of fins, each spacer defining a different shape, forming gate spacers adjacent the plurality of fins, the gate spacers directly contacting the one or more of the plurality of fins having a spacer, forming a barrier spacer between a set of fins of the plurality of fins, the barrier spacer directly contacting a top surface of a shallow trench isolation (STI) region, forming n-type epitaxial regions between the plurality of fins, forming p-type epitaxy regions over the n-type epitaxial regions, and forming a first contact extending vertically through the semiconductor device adjacent the barrier spacer and extending laterally away from the barrier spacer to directly contact a sidewall of an n-type epitaxial region.

Bottom contact for stacked GAA FET

A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor

A field effect device is provided. The field effect device includes a lower active gate structure on a substrate, and a first lower source/drain on a first side of the lower active gate structure. The field effect device further includes a second lower source/drain on a second side of the lower active gate structure opposite the first side, and a first lower source/drain contact interface on the first lower source/drain. The field effect device further includes a first upper source/drain on the first side of an upper active gate structure, and a second upper source/drain on the second side of the upper active gate structure opposite the first side. The field effect device further a shared source/drain contact forming an electrical connection between the first lower source/drain and the first upper source/drain; and a lower source/drain contact forming an electrical connection to the second lower source/drain.

Middle of line structure with stacked devices

A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

Embodiments disclosed herein describe methods of forming semiconductor devices. The methods may include etching vias and trenches in a middle-of-line (MOL) layer that has a low-k dielectric layer, a sacrificial nitride layer, and a hard mask layer. The methods may also include depositing a thin nitride layer within the via trench, depositing a carbon layer on the thin nitride layer within the vias and trenches, etching back the thin nitride layer to expose a portion of the hard mask layer, removing the hard mask layer and the carbon layer, and removing the thin nitride layer and the sacrificial nitride layer.

Hard mask removal without damaging top epitaxial layer

A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Three-dimensional field effect device

Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1over a bottom portion having a width W2, wherein W2<W1, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

Area scaling for VTFET contacts

A device includes: a first dielectric material; a first metal line in the first dielectric material; a second dielectric material disposed on the first dielectric material and the first metal line; a second metal line in the second dielectric material; and a plurality of metal vias disposed on a same level and connecting the first metal line and the second metal line, wherein the plurality of metal vias comprise a first top via and a bottom via having different sidewall profile angles.

Dual color via patterning

Semiconductor devices and methods of forming the same include forming dummy gate spacers in a trench in a semiconductor substrate. A dummy gate is formed in the trench. An exposed dummy gate spacer is replaced with a sacrificial spacer. A cap layer is formed over the dummy gate. The cap layer is etched to expose the dummy gate. The sacrificial spacer is replaced with an isolation dielectric spacer. The dummy gate is replaced with a conductor.

Self-aligned gate contact for VTFETs

A stacked device is provided. The stacked device includes a reduced height active device layer, and a plurality of lower source/drain regions in the reduced height active device layer. The stacked device further includes a lower interlayer dielectric (ILD) layer on the plurality of lower source/drain regions, and a conductive trench spacer in the lower interlayer dielectric (ILD) layer, wherein the conductive trench spacer is adjacent to one of the plurality of lower source/drain regions. The stacked device further includes a top active device layer adjacent to the lower interlayer dielectric (ILD) layer, and an upper source/drain section in the top active device layer. The stacked device further includes a shared contact in electrical connection with the upper source/drain section, the conductive trench spacer, and the one of the plurality of lower source/drain regions.

High aspect ratio shared contacts

A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

Low-resistance top contact on VTFET

A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

Sacrificial fin for self-aligned contact rail formation

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Cohoes, NY, United States of America

Su Chen Fan