Samsung Electronics Co., Ltd.

Su-a Kim

Chul-woo Park

Jae-Youn Youn

Hak-soo Yu

Hyo-jin Choi

Young-Soo Sohn

Jong-Pil Son

Hong-Sun Hwang

Hoi-ju Chung

Mu-jin Seo

Sang-Yun Kim

Young-Ho Kim

Kwang-il Park

Ki-Whan Song

Young-Ju Kim

Dae-hyun Kim

Soo-Young Kim

Chan-Kyung Kim

Dae-Jeong Kim

Hyuk-Joon Kwon

Kee-Won Kwon

Bok-Yeon Won

Hi-choon Lee

Byung-sick Moon

Sang-Keun Han

Hyun-chul Yoon

Sung-Hyun Lee

Dong-Soo Kang

Ji-Suk Kwon

Dae-Sun Kim

Kyoung-Heon Jeong

Woong-dai Kang

Bum-Jae Lee

Jun-Hee Yoo

Sung-Min Ryu

Min-Woo Won

Ji-Hak Yu

Seok-Jae Lee

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

A memory device including a memory cell array region, includes, column selection signal lines formed in a first column conduction layer of the memory cell array region and extending in a column direction, global input-output data lines formed in a second column conduction layer of the memory cell array region different from the first column conduction layer and extending in the column direction and power lines formed in a shield conduction layer of the memory cell array region between the first column conduction layer and the second column conduction layer. The noises in the signal lines and the power lines may be reduced and performance of the memory device may be enhanced by forming the column selection signal lines and the global input-output data lines in different column conduction layers and forming the power lines in the shield conduction layer between the column conduction layers.

Memory device and method of disposing conduction lines of the same

The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

Memory device capable of quickly repairing fail cell

A method of operating a volatile memory device includes storing address information of weak cell rows. According to some examples, after writing to a weak cell row, a refresh operation is performed on the weak cell row within a predetermined time. According to some examples, the writing operation to a weak cell row may be performed with a longer write recovery time than a write recovery time to normal cell rows.

Method of operating a volatile memory device and a memory controller

A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Semiconductor memory devices and memory systems including the same

A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same

In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Memory system for continuously mapping addresses of a memory module having defective locations

In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.

Semiconductor memory device and system having redundancy cells

Volatile memory device and a memory controller

Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof

A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.

Semiconductor memory device and memory system including the same

A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

Semiconductor memory device including vertical channel transistors

A method reduces a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.

Trap charge equalizing method and threshold voltage distribution reducing method

Growing community of inventors

Seongnam-si, South Korea

Su-a Kim