Semiconductor Components Industries, LLC

Stéphanie Conseil

Joel Turchi

Radim Mlcousek

A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.

Circuit for generating a clock signal for interleaved PFC stages and method thereof

A method and circuit for protecting against an over current condition. A conduction time of one or more transistors is reduced during the over current condition. The conduction time is reduced in an amount that is an increasing function of the amount of the over current. The conduction time may be reduced proportionally to the excess current.

Growing community of inventors

Colomiers, France

Stéphanie Conseil