International Business Machines Corporation

Stuart Zachary Jacobs

David Anthony Larson

Wade Byron Ouren

Kenneth Charles Vossen

Naresh Nayar

Kyle Alan Lucke

Peter Joseph Heyrman

Edward Curtis Prosser

Andrew T Koch

Michael James Vance

Bruce Gerard Mealey

David Alan Hepkin

Troy David Armstrong

William Joseph Armstrong

Richard Loise Arndt

Florian Alexander Auernhammer

Steven Leonard Roberts

Michael Joseph Corrigan

Christian Pinto

David A Larson Stanton

Jonathan Ross Van Niewaal

Kenneth Roger Allen

William Anton Brown

David Anthony Larson Stanton

Wade Bryon Ouren

Christopher Brian Wallis

A data processing system includes a system fabric, a system memory, a memory controller, and a link controller communicatively coupled to the system fabric and configured to be communicatively coupled, via a communication link to a destination host with which the source host is non-coherent. A plurality of processing units is configured to execute a logical partition and to migrate the logical partition to the destination host via the communication link. Migration of the logical partition includes migrating, via a communication link, the dataset of the logical partition executing on the source host from the system memory of the source host to a system memory of the destination host. After migrating at least a portion of the dataset, a state of the logical partition is migrated, via the communication link, from the source host to the destination host, such that the logical partition thereafter executes on the destination host.

Migration of a logical partition between mutually non-coherent host data processing systems

Within a hashed page table maintained by a hypervisor, a special host real address configured to access a hardware device using access data intended to be invalidated is identified as part of a firmware assisted dump process for a virtual machine executing on the hypervisor. The special host real address is translated to a corresponding special guest real address. Within the hashed page table, the special host real address is replaced with the corresponding special guest real address, and the corresponding special guest real address is marked as invalid and requiring special handling. Subsequent to the replacing, the special host real address is invalidated. The special guest real address and translated address information are provided to the virtual machine subsequent to the invalidating, the translated address information comprising a set of host real addresses translated to corresponding guest real addresses.

Preserving transient address translation information across a firmware assisted dump procedure

A computer-implemented method and system for affinity based optimization of persistent memory volumes. Responsive to receiving a request for a parent virtual PMEM device, a total memory capacity is apportioned amongst virtual persistent memory (PMEM) resources and physical memory resources. In accordance with a target affinity characteristic, a set of virtual central processor unit (CPU) sockets are assigned. Each virtual CPU socket is configured based on at least one physical central processor unit (CPU) core in conjunction with a subset of the virtual PMEM and physical memory resources. Child virtual PMEM devices are created for respective ones of the virtual CPU sockets, each of the child virtual PMEM devices being dedicated to the parent virtual PMEM device.

Affinity based optimization of virtual persistent memory volumes

Systems, methods, and computer program products to perform an operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt, and responsive to the lightweight HDEC interrupt, initiating an asynchronous hardware operation on the shared processor prior to completion of the dispatch cycle.

Using a decrementer interrupt to start long-running hardware operations before the end of a shared processor dispatch cycle

In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.

Affinity of virtual processor dispatching

The present disclosure includes a method for transferring checkpoint information of a primary virtual machine from a primary host to a secondary host that includes, by the primary host, capturing checkpoint information from the primary virtual machine to a primary holding buffer on the primary host, generating a first number of partition state records from the checkpoint information, transmitting the first number of partition state records to the secondary host, receiving acknowledgements from the secondary host for a second number of partition state records, and tracking the second number of partition state records acknowledged by the secondary host.

Checkpoint capture and tracking in a high availability system

A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Failover detection and treatment in checkpoint systems

A technique for handling interrupts includes receiving an event notification message (ENM) that specifies an event target number (ETN) and a number of bits to ignore (NBI). The ETN identifies a specific virtual processor thread (VPT) and the NBI identifies the number of lower-order bits of the specific VPT to ignore when determining a group of VPTs that may be potentially interrupted. In response to two or more VPTs within the group of VPTs being dispatched and operating on an associated physical processor, whether multiple of the two or more VPTs do not have a pending interrupt is determined. In response to determining that multiple of the two or more VPTs do not have a pending interrupt, one of the two or more VPTs is selected to service an interrupt associated with the ENM based, at least in part, on respective preferred bits for the two or more VPTs.

Techniques for indicating a preferred virtual processor thread to service an interrupt in a data processing system

Systems, methods, and computer program products to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

A method, system, and computer readable medium to share data on a global basis within a symmetric multiprocessor (SMP) computer system are disclosed. The method may include grouping a plurality of processor cores into a plurality of affinity groups. The method may include creating hints about the global data in the plurality of group data structures. Each group data structure may correspond to an affinity group. The method may read a first group data structure by a thread executing on a processor core associated with a first affinity group.

Affinity group access to global data

Method to perform an operation, the operation comprising processing a first logical partition on a shared processor for the duration of a dispatch cycle, issuing, by a hypervisor, at a predefined time prior to completion of the dispatch cycle, a lightweight hypervisor decrementer (HDEC) interrupt specifying a cache line address buffer location in a virtual processor, and responsive to the lightweight HDEC, writing, by the shared processor, a set of cache line addresses used by the first logical partition to the cache line address buffer location in the virtual processor.

Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Growing community of inventors

Lakeville, MN, United States of America

Stuart Zachary Jacobs