Dell USA L P

Dell Products Inc.

Stuart William Hayes

Erik A Schuchmann

Shane Michael Chiasson

Robert G Bassman

Wai-Ming Richard Chan

James Van Artsdalen

Michael Leins

Ian Timmins

Mukund Purshottam Khatri

Kevin Lee Miller

Joseph A Vivio

Charles E Rose

Richard Chan

Joshua Titus

Methods and system are provided for remote management of an IHS (Information Handling System). A keypair is generated by a client management application using operating system capabilities of the IHS. The client management application, as a privileged operating system user, writes a public key of the keypair to UEFI (Unified Extensible Firmware Interface) variables stored within a secured data storage device of the IHS. A BIOS of the IHS retrieves the public key from the UEFI variables and uses it to encrypt a remote management secret. The BIOS writes the encrypted secret back to the UEFI variables. The client management application uses the keypair to recover the remote management secret from the encrypted secret that was written to the UEFI variables by the BIOS. The secret is used to establish a secure remote management session between the client management application and a remote access controller of the IHS.

Configuring trusted remote management communications using UEFI

A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.

Method of reducing noise induced from reference plane currents

System for reducing noise induced from reference plane currents

A method and system are provided for reducing impedance discontinuities which occur when two expansion connectors are located very close to one another on a bus in an information handling system. An interconnect is situated between the two expansion connectors and exhibits an impedance which is selected to be sufficiently low to compensate for the amount by which the impedance of the expansion bus connectors exceeds the impedance of the expansion bus connected thereto.

Method and system for reducing aggregate impedance discontinuity between expansion connectors

A method and apparatus are provided for reducing impedance discontinuities which occur when two expansion connectors are located very close to one another on a bus in an information handling system. An interconnect is situated between the two expansion connectors and exhibits an impedance which is selected to be sufficiently low to compensate for the amount by which the impedance of the expansion bus connectors exceeds the impedance of the expansion bus connected thereto.

Information handling system including a bus in which impedance discontinuities associated with multiple expansion connectors are reduced

An adaptive card-sensitive bus slot system and method. The method and system include a substantially universal bus slot structure. In one embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key. In another embodiment, the substantially universal bus slot structure includes at least one Peripheral Component Interconnect adaptive key piston. In another embodiment, a data processing system includes the adaptive card-sensitive bus slot system.

Adaptive card-sensitive bus slot method and system

A method and system for utilizing a single motherboard connector to allow connecting to one of two storage devices having different interfaces. The motherboard of a computer system includes, either as a single circuit or as a multi-function ship, an IDE controller that is operable to interface with a storage device that uses the IDE interface. The motherboard also includes a SCSI controller that is operable to interface with a storage device that uses the SCSI interface. Both controllers are coupled to a connector on the motherboard. The connector is configured to engage a SCSI interface device. The connector is coupled to one end ( ) of a cable. The cable includes a second connection point ( ) that is configured to engage an IDE interface device.

Method and system for connecting dual storage interfaces

A filter circuit for filtering bus accesses from a computer bus (such as e.g. a bus conforming to the PCI standard) to a group of devices operably coupled to the computer bus in a computer system. The filter circuit operates in a filter mode and a non filter mode. In the non filter mode, the filter circuit allows bus accesses to pass from the computer bus to the group. In the filter mode, the filter circuit blocks bus accesses from passing to the group. Upon determining that a bus access is an allowable bus access, the filter circuit initiates a retry request to signal the bus master that initiated the allowable bus access to reinitiate the bus access, wherein the filter circuit allows the allowable bus access to pass to the group. The filter circuit includes a switch circuit and a control circuit that places the switch circuit in the conductive and non conductive switch states to allow bus accesses to pass and to be blocked from passing to the group, respectively. In the filter mode, the filter circuit allows bus accesses to pass from a device of the group to the computer bus. The filter circuit includes a second switch circuit for controlling the bus accesses by the device of the group. The control circuit includes a programmable logic device. The filter circuit can be used in debugging a computer system which has a malfunctioning flash ROM. A second flash ROM can be inserted into a PCI slot and the filter circuit activated to filter accesses directed towards the malfunctioning flash ROM during the boot-up of the computer system.

Filter-circuit for computer system bus

Adapter cards generally have a metal bracket at one end. The adapter card attaches to an adapter card slot of a computer system by fastening the bracket to a connector on the computer system. Conventionally, the bracket is fastened to the connector using a screw. It has been discovered that an electrically-conductive flip-down retainer advantageously functions as an improved fastener to secure the adapter card to the connector. The electrically-conductive flip-down retainer is a single structure that performs the combined functions of an electrical switch and a mechanical fastener. The electrically-conductive flip-down retainer includes electrical contacts that form a closed circuit when the bracket is fastened to the connector and an open circuit when the bracket is not fastened. The electrical contacts are connected to conductors extending to a controller. The controller monitors the status of the electrical switch of the electrically-conductive flip-down retainer and controls application of power to the adapter card slot, typically under control of an operating system. The controller terminates power to the adapter card slot when the electrically-conductive flip-down retainer is unfastened, indicating that the adapter card is disengaged from the adapter card slot. The controller restores power to the adapter card slot when the electrically-conductive flip-down retainer is fastened, indicating the adapter card is engaged with the adapter card slot.

Hot-plug interface for detecting adapter card insertion and removal

A switch is disclosed for indicating that a computer card is installed in an expansion slot of a computer. A conductive strip attaches to an end wall of the slot and deforms when a computer card is installed. A conductive contact is provided in the wall of the slot to complete an electrical connection when the conductive strip is deformed. The strip connects electrically to a conductor that is passively driven high by a voltage source and pull-up resistor. The contact connects electrically to ground, so that when the computer card causes the strip to touch the contact, the voltage on conductor is driven low, providing an indication to associated circuitry that a card is present in the slot. A pair of switches may be used to provide repetitive signals indicating a card is present. If only one switch is closed, the computer may indicate to the user that a card has been installed improperly, or contaminants are present in the slot.

Slot for mechanically detecting the presence of a computer card

A system and method for disabling and re-enabling peripheral devices (PDs) in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a host-bus-to-peripheral-device-bus (HB/PDB) bridge coupled to the host bus, at least one PD, at least one peripheral device bus coupling the HB/PDB bridge and at least one PD, and a device, typically in the form of a digital gate, for selectively disabling and re-enabling at least one PD. The disclosed method operates in connection with a computer system having a CPU, a HB/PDB bridge coupled to the CPU and capable of sending a device-configuration-space-access-signal (DCSAS) to the DCSAS input pin of a target PD when attempting an access operation, such as a read or a write operation, on the target PD, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PD. The method intercepts the DCSAS before it reaches the DCSAS input pin of the target PD, provides the intercepted DCSAS to the input of a digital gate such as an AND gate, provides a signal corresponding to the CONFIG ENABLE bit to the input of the same digital gate, and delivers the resulting output signal from the digital gate to the DCSAS input pin of the target PD.

System and method for disabling and re-enabling at least one peripheral

It has been discovered that providing a computer system with a hot pluggable power supply as well as a disconnectable resistive load allows a second power supply to be brought on-line while operating within the proper voltage range and then disconnecting the resistive load from the power supply so as to conserve energy and lower the operating temperature of the computer system. Such a system also conserves energy by reducing the size of the fan that the computer system requires. Such a system also allows for a the use of larger test resistor thus providing a more accurate load test. Such a system also allows for saving space as one test circuit can be used for both power supplies. Such a system also allows for a reduced capacity power supply as the power supply does not have to continuously supply power to the resistive test load.

Method for making redundant power supplies hot-pluggable

The present invention provides a computer system which electronically and automatically detects the maximum rated operating frequency of a microprocessor installed in the computer system. The present invention also electronically and automatically detects, selects and generates a 'common' external/internal operating clock frequency in a multiprocessor system when more than one microprocessor is installed in the computer system. More particularly, a computer system is disclosed which includes at least one microprocessor and a main memory coupled to each microprocessor. Each microprocessor includes an electronic stamp with a value of a maximum rated operating frequency for the microprocessor written therein. The computer system includes a clock generating section for electronically detecting the value of the maximum rated operating frequency of the each microprocessor and for selecting and generating an operating frequency for the computer system. In one embodiment of the present invention, the electronic stamp on each microprocessor includes a nonvolatile memory module, such as an electrically erasable reprogrammable nonvolatile memory, coupled to each microprocessor with the value of the maximum rated operating frequency of the microprocessor stored in, for example, a register. In another embodiment of the present invention, the electronic stamp on each microprocessor includes an encoded strapping circuit integrated into each microprocessor which provides the value of the maximum rated operating frequency in an electronically coded form, such as pins on the microprocessor with a coded setup.

Process to allow automatic microprocessor clock frequency detection and

The present application describes a tuned guard circuit device and method for controlling impedance levels of transmission lines on a printed circuit board having at least one ground plane and at least two circuit components coupled by a conductive transmission line. The guard circuit device of the present invention includes two etched conducting guard bands on the printed circuit board disposed on opposite sides of a selected transmission line and affixed in a spaced parallel relation to the transmission line. The guard bands are of substantially constant width and substantially constant distance from the ground plane and have substantially the same length as the transmission line, and each guard band has a first and a second terminal end. Also included is a capacitor connected to the ground plane and connected at each of the first and second terminal ends of each guard band wherein the guard bands are connected to ground through the capacitors. The guard circuit device controls the impedance level of the transmission line by varying the capacitance values of the capacitors to optimize the impedance level of the transmission line. The capacitance values of all the capacitors are, preferably, equal.

Growing community of inventors

Austin, TX, United States of America

Stuart William Hayes