Intersil Corporation

Red Chip Company Ltd.

Stuart W Pullen

Donald R Preslar

William R Young

Patrick Anthony Begley

Michael M Walters

Harold A Witlinger

John Ulrick

An output stage for a class D amplifier reduces distortion and EMI, and greatly improves the efficiency. The output stage employs a combination of techniques including a soft switching network, multiple output inductors and beads to achieve, a high power full range class D amplifier that is complies with all FCC and CE specifications with greater than 90% efficiency at &frac13; power.

Output stage for high power class D amplifiers

The frequency spectrum of variable frequency class D modulator interferes with RF signals in the AM bandwidth. Here several techniques solve the problem including an amplifier that synchronizes an external clock input the summing node of the integrator, an amplifier that gates an external clock to the modulator using a transmission gate that responds to the AM frequency, and an amplifier that adjusts its own hysteresis to provide a clock that does not interfere with AM input signals.

Techniques for synchronizing a self oscillating variable frequency modulator to an external clock

A high Q low pass filter removes the carrier from a Class D amplifier. Speaker impedance varies with frequency, and it is desirable for to drive 2, 4 and 8 ohm speakers. The bandwidth feedback compensation network,adds a pole-zero combination to the feedback loop to reduce the Q of the low pass filter and to maintain the bandwidth of the amplifier.

Class D amplifier with bandwidth independent of load impedance

The low jitter dead time circuit which uses one RC combination to set the turn on delay for both the upper and lower MOSFETs in the half bridge. This circuit minimized jitters in the turn on delay and results in matched turn on delays for both MOSFETs in a half bridge. This minimizes noise and distortion. This circuit is further designed to be used in conjunction with shunt regulators to reject ripple from the power supplies.

Low noise low distortion class D amplifier

The OCL,receives two logic signals: the first, OC upper FET, is high when an over current condition exists in the upper FET,; the second, OC lower FET, is high when an over current condition exists in the lower FET,. When the over current condition is in FET,, PMOS,turns on and injects current into the summing junction of the integrator,through Rcl. The net effect is turn off the upper FET,and turn on the lower FET,. This reduces the current in FET,. As far as amplifier,is concerned, the net effect is gain compression. Since upper FET,is on less and the lower FET,is on more, the gain of the audio signal is reduced. When the over current condition is in FET,, NMOS,turns on and pulls current out of the summing junction, turns the lower FET,off, and turns the upper FET,on. The net effect is to reduce the current in the lower FET. At audio frequencies, the gain is reduced.

Class D modulator with peak current limit and load impedance sensing circuits

Load-monitoring feedback is used to maintain the slew rate of a line driver circuit at a prescribed rate that is independent of the effective load of the line being driven. This load-monitoring feedback control makes it possible to drive the line with an amplified output signal that faithfully tracks the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of characteristics of the signal line, which may vary over a specified range of component values. In a first embodiment, slew rate control is effected by increasing or decreasing the amount of charge on a reference capacitor and thereby the drive current to an output driver FET, in accordance with the change in state of the output of an output terminal-monitoring voltage threshold comparator relative to termination of a prescribed (one-shot established) time window. In a second embodiment, slew rate control is effected by directly determining the length of time required for the output terminal to transition between first and second states, and adjusting the operation of the output driver FET based on whether the total time measurement is equal to, greater than or less than the slew rate window.

Driver circuit having load-independent slew rate

A class D modulator 100 is self oscillating. It includes an input stage 110, an operational amplifier 120, an integrator 130 and a pulse width modulator 140. A start-up generator 22 generates signals ENABLE and MUTE. The MUTE signal is connected to the input stage 110 to prevent any unwanted, initial sound. The ENABLE signal connects a start-up voltage source to the integrator 130 to set the initial voltage for integration. The ENABLE signal is coupled to a dead time control circuit 16 which controls the operation of the output power transistors 42, 44 to assure that the low side power transistor 44 is turned on before the high side transistor 42.

Start-up circuit for self oscillating class D modulator

A sensing circuit 100 includes two resistors 11 and 12, two pnp transistors 13 and 14, and a current mirror 15 and 16. Resistors 11 and 12 convert the high voltages present in the bridge into a proportional current. The current mirror, mosfets 15 and 16, compares I.sub.1 and I.sub.2. If I.sub.2 is greater than I.sub.1 the voltage at point A is high. Otherwise this voltage is low. Resistor 12 is chosen smaller than 11 so that under normal operation, when FET 22 turns on, I.sub.2 is greater than I.sub.1 and the voltage at point A is high. During an overcurrent event, the drop across the FET 22, Von, is so great that I.sub.2 is less than I.sub.1 and the voltage a point A stays low.

Overcurrent sensing circuit and self adjusting blanking

A class D amplifier 100 has an integrator 10, a comparator 12, and a frequency compensation and gain control (FCGC) circuit 40. The FCGC circuit 40 senses the output and reduces the gain in order to keep the sampling frequency high enough to avoid audio artifacts.

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Raleigh, NC, United States of America

Stuart W Pullen