Other

Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Arm Limited

Transmeta Corporation

Stuart Siu

Steven Thomas Stoiber

Joseph Ku

Padmanabha I Venkitakrishnan

Shankar Venkataraman

Paul S Keltcher

Betina Hold

Stephen Richardson

Gary Vondran

In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Ring based impedance control of an output driver

One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

A signal linehas at a first location a first driverto drive a first signal level on that signal line. A second driveris provided at a second location, separated from the first location, and serves to drive the line signal to a different value from that driven by the first driver. Associated with each of these driversare respective keeper circuitsserving to maintain the signal value driven by the respective remote driver. Thus, the first keeperlocal to the first driverserves to maintain the signal value driven by the second driver. The keepersare disabled by the control signal which enables their local driverand thus do not contend with the change being driven by their local driver

Controlling signal levels on a signal line within an integrated circuit

A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states (modified, shared, and invalid) and three intermediate memory unit pending states. The pending states are used by the present invention to prevent race conditions that may develop during the completion of a transaction. The pending states 'lock out' the memory unit (e.g., prevent access by other agents to a cache line) whose state is in transition between two primary states, thus ensuring coherency protocol correctness. Transitions between states are governed by a series of request and reply or acknowledgment messages. The memory unit is placed in a pending state while appropriate measures are taken to ensure access takes place at an appropriate time. For example, a modification occurs only when other agents can not access the particular memory unit (e.g., a cache line).

Streamlined cache coherency protocol system and method for a multiple processor single chip device

Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.

Chip multiprocessor with multiple operating systems

A power efficient flip-flop includes a power switch regulating power supplied to a high speed latch in the flip-flop. When the power switch is activated, causing the high speed latch to receive power, the high speed latch captures data received by the flip-flop. The captured data is propagated by the high speed latch to the output of the flip-flop. Simultaneously, the high speed latch transmits the data to a low leakage latch connected to the high speed latch. Then, power is removed from the high speed latch, and the data retained in the low leakage static latch is now released to the output of the flip-flop. The power efficient flip-flop minimizes leakage current generated by the high speed latch by removing a path to ground when power is not provided to the high speed latch. A decoupling device is connected to the power switch to substantially eliminate a coupling effect.

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Castro Valley, CA, United States of America

Stuart Siu