Itt Manufacturing Enterprises, Inc.

Stuart Mitchell Lopata

James B Y Tsui

Charles Richard Ward

Maan J Broadstock

An instantaneous frequency measurement (IFM) receiver includes a receiver module for determining a frequency fof a received signal. Also included is a discrete Fourier transform (DFT) module configured to sum values of digital samples of data in a block of data, wherein the values of the digital samples of data are based on the frequency f. A confirmation module confirms the frequency f, if the sum has a value greater than a predetermined threshold. The DFT module is configured to obtain the sum of N-sample points of data which are disposed in the block of data by using a DFT kernel function.

Detection and time-of-arrival estimation using an IFM receiver

An apparatus for confirming a frequency measurement of a received signal includes a discrete Fourier transform (DFT) module for receiving a sampled digital signal. The DFT module is configured to analyze the received sampled digital signal, and output amplitude values at different frequency components. A threshold comparator is included for receiving the amplitude values of the frequency components and outputting a thresholded-amplitude value exceeding a predetermined threshold value. A frequency confirmation is provided based on the thresholded-amplitude value. The sampled digital signal is sampled at a sampling frequency of f, and the DFT module is configured to analyze the received sampled digital signal at a frequency bandwidth that is equal to or less than f. The frequency bandwidth is equal to the sampling frequency of f, when the received sampled digital signal includes I and Q signals. The DFT module is configured to analyze the received sampled digital signal by examining N frequency components, where N equals the total number of frequency components equally spaced between 0 and the sampling frequency.

Wideband digital IFM receiver with frequency confirmation

An IFM receiver includes a hybrid for outputting I and Q signals from a received input signal; a first ADC for digitizing the I signal to produce a first digital signal at a sampling rate of 1/&#x3c4;, and a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate. A processor is configured to (a) delay the first and second digital signals by at least one sample time of &#x3c4;, (b) count the number of samples produced having predetermined phase shifts, and (c) determine the frequency of the received input signal, based on the number of samples having the predetermined phase shifts. The first and second ADCs are each 1-bit analog-to-digital converters. The predetermined phase shifts of 0&#xb0;, 90&#xb0;, &#x2212;90&#xb0; and 180&#xb0; are counted by the processor over a predetermined time interval.

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Palisades Park, NJ, United States of America

Stuart Mitchell Lopata