Dialog Semiconductor Gmbh

Sony United Kingdom Limited

Stuart Levine

Julian Tyrrell

Anna Hedley

David Clewett

Biren Minhas

Keith Robert Calder

Nordine Chaibelaine

A control logic of a switched DC-to-DC converter allows continuous switching to bring the DC-to-DC converter to a final output value during a startup phase, it allows skipping of clock switching pulses if they are not needed and allows burst mode of switching pulses dependent on a load applied to the output voltage of the DC-to-DC converter. No digital or analog regulator is required for the control logic.

DC-DC converter efficiency improvement and area reduction using a novel switching technique

Circuits and methods to operate an arrangement of one or more charge pumps with two or more power supplies where each supply is able to vary over a range of voltages, and where any one supply can be of a higher or lower voltage than any of the others have been achieved. In a preferred embodiment the output of the arrangement of charge pumps is used to drive an electronic display. The strongest power supply available is selected and the arrangement of one or more charge pumps is reconfigured according to the value of the actual strongest supply voltage. In case of a change of a source of supply voltage the operation of the charge pumps during the short time required for reconfiguration. While the charge pump is running it can be suspended, reconfigured and released or restarted in the case of a change of supply source, or simply reconfigured on-the-fly without suspending in the case of a selected supply voltage change.

Autonomous control of multiple supply voltage generators for display drivers

A compression and de-compression arrangement is provided for a display device having a display memory and a display. The arrangement includes a color processor which reduces the color samples by processing a pair of pixels to produce first and second luminance values and forming first and second output chrominance values from the pair of pixels. The first and second output chrominance values are formed by calculating for each pixel the corresponding U and V chrominance values and forming the first and second chrominance values (U, V) from the average of the values for each pixel. Forming the compressed representation of the color image provides an advantage when recovering the original image, particularly for example where the image contains detail and/or text. The image processing apparatus of the system receives the group of color component signal samples from the display memory and generates first and second output pixels, each comprising three color component values (R, G, B), from each group. The image processing apparatus includes a detail detection processor, which detects whether either of the pixels represented by each group of signal samples represents white or black and the other does not. This may be representative of one of the pixels being part of a text character or detail. Accordingly, in order to improve the likelihood of preserving the text and detail in the reproduced image, the de-compressing processor is arranged to assign the chrominance values (U, V) of one of the pixels to zero. The other chrominance value (U, V) of the other pixel is assigned the value of twice the value of the first and second input chrominance values respectively.

Image processing apparatus and method

Growing community of inventors

Stockbridge, United Kingdom

Stuart Levine