Analog Devices,inc.

Analog Devices International Unlimited Company

Stuart John McCracken

Kimo Tam

Daniel J Mulcahy

Pablo Acosta-Serafini

John G Kenney

Mohamed Abdelsalam

Mohamed El-Nozahi

Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output.

Multi-chip programming for phased array

Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.

Apparatus and methods for clock and data recovery

Apparatus and methods are disclosed, such as those involving a receiver device. One such apparatus includes an equalizer configured to process an input signal transmitted over a channel. The equalizer can include a programmable gain amplifier (PGA) block which includes an input node configured to receive the input signal; an output node; and a programmable gain amplifier (PGA). The PGA amplifies the input signal with an adjustable gain. The PGA block also includes a gain control block having an input electrically coupled to the input node. The gain control block is configured to adjust the gain of the PGA at least partly in response to the input signal from the input node such that the PGA generates an output signal with a substantially constant amplitude envelope to the output node.

Methods for digitally-controlled automatic gain amplification

Apparatus and method for digitally-controlled automatic gain amplification

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Arlington, MA, United States of America

Stuart John McCracken