Nvidia Corporation

Advanced Micro Devices Corporation

Nishan Systems, Inc.

Brocade Communications Systems, Inc.

Stuart F Oberman

Ming Yiu Siu

Norbert Juffa

Brett Coon

John Erik Lindholm

Jack H Choquette

Jonah Matthew Alben

Brent Ralph Boswell

Ming Siu

Frederick Daniel Weber

Stephan G Meier

Rodney Norman Mullendore

Peter C Mills

Anil Mehta

Kamran Malik

Keith R Schakel

David Conrad Tannenbaum

Matthew P Gerlach

Fred Weber

John R Nickolls

Ravikrishna Cherukuri

Andrew Robert Kerr

Jeffrey Michael Pool

John Tran

Samuel Kan Liu

Srinivasan Iyer

Weizhong Xu

Krishnan V Ramani

Colin Sprinkle

Ravi Krishna Cherukuri

Scott A White

Henry Packard Moreton

Steven E Molnar

Shirish C Gadre

John Matthew Burgess

Michael C Shebanow

Alexander Lev Minkin

Peter B Holmqvist

Michael Alan Fetterman

Ilyas Elkin

Xiaogang Qiu

Bryan Catanzaro

Robert J Stoll

Paul S Heckbert

Jeffrey E Trull

Yan Yan Tang

Sameer Halepete

Ian Chi Yan Kwong

Jered Wierzbicki

Mark E Roberts

Srinivasan (Vasu) Iyer

Ravi Krishna

Manu Gulati

Rajarshi Roy

Jonathan Raiman

Ian-Chi Yan Kwong

Neel Kant

Saad Godil

Robert Kirby

Ming (Michael) Y Siu

A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.

Inline data inspection for workload simplification

Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.

Data path circuit design using reinforcement learning

A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Generalized acceleration of matrix multiply accumulate operations

A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations.

Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations

A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well as a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.

Dispatching a stored instruction in response to determining that a received instruction is of a same instruction type

A method, computer readable medium, and system are disclosed for inline data inspection. The method includes the steps of receiving, by a load/store unit, a load instruction and obtaining, by an inspection circuit that is coupled to the load/store unit, data specified by the load instruction. Additional steps include determining that the data equals zero and transmitting the data and a predicate signal to the load/store unit, wherein the predicate signal indicates that the data equals zero. Alternative additional steps include computing a predicate value based on a comparison between the data and a threshold value and transmitting the data and the predicate value to the load/store unit, wherein the predicate value is asserted when the data is less than the threshold value and is negated when the data is not less than the threshold value.

Growing community of inventors

Sunnyvale, CA, United States of America

Stuart F Oberman